[llvm] [ARM][ISel] Fix crash of ISD::FMINNUM/FMAXNUM (PR #65849)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 12 04:56:11 PDT 2023
https://github.com/vfdff updated https://github.com/llvm/llvm-project/pull/65849:
>From a6772a0aacf3a6769a316c1d4b59b63044fe03e8 Mon Sep 17 00:00:00 2001
From: zhongyunde 00443407 <zhongyunde at huawei.com>
Date: Sat, 9 Sep 2023 07:27:20 -0400
Subject: [PATCH 1/2] [ARM][ISel] Fix crash of ISD::FMINNUM/FMAXNUM
Set ISD::FMINNUM/FMAXNUM legal when feature HasV8 is set.
Fixes https://github.com/llvm/llvm-project/issues/65820
---
llvm/lib/Target/ARM/ARMISelLowering.cpp | 2 +-
.../CodeGen/ARM/minnum-maxnum-intrinsics.ll | 42 +++++++++++++++++++
2 files changed, 43 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 80a1476660947e0..c483f52f5186388 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -1504,7 +1504,7 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::FRINT, MVT::f32, Legal);
setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
- if (Subtarget->hasNEON()) {
+ if (Subtarget->hasNEON() && Subtarget->hasV8Ops()) {
setOperationAction(ISD::FMINNUM, MVT::v2f32, Legal);
setOperationAction(ISD::FMAXNUM, MVT::v2f32, Legal);
setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal);
diff --git a/llvm/test/CodeGen/ARM/minnum-maxnum-intrinsics.ll b/llvm/test/CodeGen/ARM/minnum-maxnum-intrinsics.ll
index e17075d067c26bd..6d17faadd3d4ff7 100644
--- a/llvm/test/CodeGen/ARM/minnum-maxnum-intrinsics.ll
+++ b/llvm/test/CodeGen/ARM/minnum-maxnum-intrinsics.ll
@@ -1456,3 +1456,45 @@ define <2 x double> @fmaxnumv264_non_zero_intrinsic(<2 x double> %x) {
%a = call nnan <2 x double> @llvm.maxnum.v2f64(<2 x double> %x, <2 x double><double 1.0, double 1.0>)
ret <2 x double> %a
}
+
+define void @pr65820(ptr %y, <4 x float> %splat) {
+; ARMV7-LABEL: pr65820:
+; ARMV7: @ %bb.0: @ %entry
+; ARMV7-NEXT: vmov d16, r2, r3
+; ARMV7-NEXT: vdup.32 q8, d16[0]
+; ARMV7-NEXT: vcgt.f32 q9, q8, #0
+; ARMV7-NEXT: vand q8, q8, q9
+; ARMV7-NEXT: vst1.32 {d16, d17}, [r0]
+; ARMV7-NEXT: bx lr
+;
+; ARMV8-LABEL: pr65820:
+; ARMV8: @ %bb.0: @ %entry
+; ARMV8-NEXT: vldr s0, .LCPI33_0
+; ARMV8-NEXT: vmov s2, r2
+; ARMV8-NEXT: vmaxnm.f32 s0, s2, s0
+; ARMV8-NEXT: vstr s0, [r0]
+; ARMV8-NEXT: vstr s0, [r0, #4]
+; ARMV8-NEXT: vstr s0, [r0, #8]
+; ARMV8-NEXT: vstr s0, [r0, #12]
+; ARMV8-NEXT: mov pc, lr
+; ARMV8-NEXT: .p2align 2
+; ARMV8-NEXT: @ %bb.1:
+; ARMV8-NEXT: .LCPI33_0:
+; ARMV8-NEXT: .long 0x00000000 @ float 0
+;
+; ARMV8M-LABEL: pr65820:
+; ARMV8M: @ %bb.0: @ %entry
+; ARMV8M-NEXT: vmov d0, r2, r3
+; ARMV8M-NEXT: vmov r1, s0
+; ARMV8M-NEXT: vmov.i32 q0, #0x0
+; ARMV8M-NEXT: vdup.32 q1, r1
+; ARMV8M-NEXT: vmaxnm.f32 q0, q1, q0
+; ARMV8M-NEXT: vstrw.32 q0, [r0]
+; ARMV8M-NEXT: bx lr
+entry:
+ %broadcast.splat = shufflevector <4 x float> %splat, <4 x float> zeroinitializer, <4 x i32> zeroinitializer
+ %0 = fcmp ogt <4 x float> %broadcast.splat, zeroinitializer
+ %1 = select <4 x i1> %0, <4 x float> %broadcast.splat, <4 x float> zeroinitializer
+ store <4 x float> %1, ptr %y, align 4
+ ret void
+}
>From ff34be751f6fc7fe37880afa4d09380b629ed352 Mon Sep 17 00:00:00 2001
From: zhongyunde 00443407 <zhongyunde at huawei.com>
Date: Mon, 11 Sep 2023 22:10:54 -0400
Subject: [PATCH 2/2] Fix comment, Requires<[HasFPARMv8, HasNEON]>
---
llvm/lib/Target/ARM/ARMISelLowering.cpp | 2 +-
llvm/lib/Target/ARM/ARMInstrNEON.td | 16 +-
.../CodeGen/ARM/minnum-maxnum-intrinsics.ll | 392 ++++++++++++++++++
3 files changed, 401 insertions(+), 9 deletions(-)
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index c483f52f5186388..7f8753aa9c031a4 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -1504,7 +1504,7 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::FRINT, MVT::f32, Legal);
setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
- if (Subtarget->hasNEON() && Subtarget->hasV8Ops()) {
+ if (Subtarget->hasNEON() && Subtarget->hasFPARMv8Base()) {
setOperationAction(ISD::FMINNUM, MVT::v2f32, Legal);
setOperationAction(ISD::FMAXNUM, MVT::v2f32, Legal);
setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal);
diff --git a/llvm/lib/Target/ARM/ARMInstrNEON.td b/llvm/lib/Target/ARM/ARMInstrNEON.td
index 9cc083a220c0154..f31e1e9f97892fa 100644
--- a/llvm/lib/Target/ARM/ARMInstrNEON.td
+++ b/llvm/lib/Target/ARM/ARMInstrNEON.td
@@ -5711,19 +5711,19 @@ let PostEncoderMethod = "NEONThumb2V8PostEncoder", DecoderNamespace = "v8NEON" i
def NEON_VMAXNMNDf : N3VDIntnp<0b00110, 0b00, 0b1111, 0, 1,
N3RegFrm, NoItinerary, "vmaxnm", "f32",
v2f32, v2f32, fmaxnum, 1>,
- Requires<[HasV8, HasNEON]>;
+ Requires<[HasFPARMv8, HasNEON]>;
def NEON_VMAXNMNQf : N3VQIntnp<0b00110, 0b00, 0b1111, 1, 1,
N3RegFrm, NoItinerary, "vmaxnm", "f32",
v4f32, v4f32, fmaxnum, 1>,
- Requires<[HasV8, HasNEON]>;
+ Requires<[HasFPARMv8, HasNEON]>;
def NEON_VMAXNMNDh : N3VDIntnp<0b00110, 0b01, 0b1111, 0, 1,
N3RegFrm, NoItinerary, "vmaxnm", "f16",
v4f16, v4f16, fmaxnum, 1>,
- Requires<[HasV8, HasNEON, HasFullFP16]>;
+ Requires<[HasFPARMv8, HasNEON, HasFullFP16]>;
def NEON_VMAXNMNQh : N3VQIntnp<0b00110, 0b01, 0b1111, 1, 1,
N3RegFrm, NoItinerary, "vmaxnm", "f16",
v8f16, v8f16, fmaxnum, 1>,
- Requires<[HasV8, HasNEON, HasFullFP16]>;
+ Requires<[HasFPARMv8, HasNEON, HasFullFP16]>;
}
// VMIN : Vector Minimum
@@ -5753,19 +5753,19 @@ let PostEncoderMethod = "NEONThumb2V8PostEncoder", DecoderNamespace = "v8NEON" i
def NEON_VMINNMNDf : N3VDIntnp<0b00110, 0b10, 0b1111, 0, 1,
N3RegFrm, NoItinerary, "vminnm", "f32",
v2f32, v2f32, fminnum, 1>,
- Requires<[HasV8, HasNEON]>;
+ Requires<[HasFPARMv8, HasNEON]>;
def NEON_VMINNMNQf : N3VQIntnp<0b00110, 0b10, 0b1111, 1, 1,
N3RegFrm, NoItinerary, "vminnm", "f32",
v4f32, v4f32, fminnum, 1>,
- Requires<[HasV8, HasNEON]>;
+ Requires<[HasFPARMv8, HasNEON]>;
def NEON_VMINNMNDh : N3VDIntnp<0b00110, 0b11, 0b1111, 0, 1,
N3RegFrm, NoItinerary, "vminnm", "f16",
v4f16, v4f16, fminnum, 1>,
- Requires<[HasV8, HasNEON, HasFullFP16]>;
+ Requires<[HasFPARMv8, HasNEON, HasFullFP16]>;
def NEON_VMINNMNQh : N3VQIntnp<0b00110, 0b11, 0b1111, 1, 1,
N3RegFrm, NoItinerary, "vminnm", "f16",
v8f16, v8f16, fminnum, 1>,
- Requires<[HasV8, HasNEON, HasFullFP16]>;
+ Requires<[HasFPARMv8, HasNEON, HasFullFP16]>;
}
// Vector Pairwise Operations.
diff --git a/llvm/test/CodeGen/ARM/minnum-maxnum-intrinsics.ll b/llvm/test/CodeGen/ARM/minnum-maxnum-intrinsics.ll
index 6d17faadd3d4ff7..d23311f7e60fcde 100644
--- a/llvm/test/CodeGen/ARM/minnum-maxnum-intrinsics.ll
+++ b/llvm/test/CodeGen/ARM/minnum-maxnum-intrinsics.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=armv7 -mattr=+neon %s -o - | FileCheck %s --check-prefix=ARMV7
+; RUN: llc -mtriple=armv7 -mattr=+fp-armv8 %s -o - | FileCheck %s --check-prefix=ARMV7-FP
; RUN: llc -mtriple=armv8.2-a -mattr=+fp-armv8 %s -o - | FileCheck %s --check-prefix=ARMV8
; RUN: llc -mtriple=armv8.1m-none-none-eabi -mattr=+mve.fp,+fp64 %s -o - | FileCheck %s --check-prefix=ARMV8M
@@ -23,6 +24,14 @@ define float @fminnum32_intrinsic(float %x, float %y) {
; ARMV7-NEXT: vmov r0, s2
; ARMV7-NEXT: bx lr
;
+; ARMV7-FP-LABEL: fminnum32_intrinsic:
+; ARMV7-FP: @ %bb.0:
+; ARMV7-FP-NEXT: vmov s0, r1
+; ARMV7-FP-NEXT: vmov s2, r0
+; ARMV7-FP-NEXT: vminnm.f32 s0, s2, s0
+; ARMV7-FP-NEXT: vmov r0, s0
+; ARMV7-FP-NEXT: bx lr
+;
; ARMV8-LABEL: fminnum32_intrinsic:
; ARMV8: @ %bb.0:
; ARMV8-NEXT: vmov s0, r1
@@ -53,6 +62,14 @@ define float @fminnum32_nsz_intrinsic(float %x, float %y) {
; ARMV7-NEXT: vmov r0, s2
; ARMV7-NEXT: bx lr
;
+; ARMV7-FP-LABEL: fminnum32_nsz_intrinsic:
+; ARMV7-FP: @ %bb.0:
+; ARMV7-FP-NEXT: vmov s0, r1
+; ARMV7-FP-NEXT: vmov s2, r0
+; ARMV7-FP-NEXT: vminnm.f32 s0, s2, s0
+; ARMV7-FP-NEXT: vmov r0, s0
+; ARMV7-FP-NEXT: bx lr
+;
; ARMV8-LABEL: fminnum32_nsz_intrinsic:
; ARMV8: @ %bb.0:
; ARMV8-NEXT: vmov s0, r1
@@ -83,6 +100,14 @@ define float @fminnum32_non_zero_intrinsic(float %x) {
; ARMV7-NEXT: vmov r0, s0
; ARMV7-NEXT: bx lr
;
+; ARMV7-FP-LABEL: fminnum32_non_zero_intrinsic:
+; ARMV7-FP: @ %bb.0:
+; ARMV7-FP-NEXT: vmov.f32 s0, #-1.000000e+00
+; ARMV7-FP-NEXT: vmov s2, r0
+; ARMV7-FP-NEXT: vminnm.f32 s0, s2, s0
+; ARMV7-FP-NEXT: vmov r0, s0
+; ARMV7-FP-NEXT: bx lr
+;
; ARMV8-LABEL: fminnum32_non_zero_intrinsic:
; ARMV8: @ %bb.0:
; ARMV8-NEXT: vmov.f32 s0, #-1.000000e+00
@@ -113,6 +138,14 @@ define float @fmaxnum32_intrinsic(float %x, float %y) {
; ARMV7-NEXT: vmov r0, s2
; ARMV7-NEXT: bx lr
;
+; ARMV7-FP-LABEL: fmaxnum32_intrinsic:
+; ARMV7-FP: @ %bb.0:
+; ARMV7-FP-NEXT: vmov s0, r1
+; ARMV7-FP-NEXT: vmov s2, r0
+; ARMV7-FP-NEXT: vmaxnm.f32 s0, s2, s0
+; ARMV7-FP-NEXT: vmov r0, s0
+; ARMV7-FP-NEXT: bx lr
+;
; ARMV8-LABEL: fmaxnum32_intrinsic:
; ARMV8: @ %bb.0:
; ARMV8-NEXT: vmov s0, r1
@@ -143,6 +176,14 @@ define float @fmaxnum32_nsz_intrinsic(float %x, float %y) {
; ARMV7-NEXT: vmov r0, s2
; ARMV7-NEXT: bx lr
;
+; ARMV7-FP-LABEL: fmaxnum32_nsz_intrinsic:
+; ARMV7-FP: @ %bb.0:
+; ARMV7-FP-NEXT: vmov s0, r1
+; ARMV7-FP-NEXT: vmov s2, r0
+; ARMV7-FP-NEXT: vmaxnm.f32 s0, s2, s0
+; ARMV7-FP-NEXT: vmov r0, s0
+; ARMV7-FP-NEXT: bx lr
+;
; ARMV8-LABEL: fmaxnum32_nsz_intrinsic:
; ARMV8: @ %bb.0:
; ARMV8-NEXT: vmov s0, r1
@@ -177,6 +218,18 @@ define float @fmaxnum32_zero_intrinsic(float %x) {
; ARMV7-NEXT: .LCPI5_0:
; ARMV7-NEXT: .long 0x00000000 @ float 0
;
+; ARMV7-FP-LABEL: fmaxnum32_zero_intrinsic:
+; ARMV7-FP: @ %bb.0:
+; ARMV7-FP-NEXT: vldr s0, .LCPI5_0
+; ARMV7-FP-NEXT: vmov s2, r0
+; ARMV7-FP-NEXT: vmaxnm.f32 s0, s2, s0
+; ARMV7-FP-NEXT: vmov r0, s0
+; ARMV7-FP-NEXT: bx lr
+; ARMV7-FP-NEXT: .p2align 2
+; ARMV7-FP-NEXT: @ %bb.1:
+; ARMV7-FP-NEXT: .LCPI5_0:
+; ARMV7-FP-NEXT: .long 0x00000000 @ float 0
+;
; ARMV8-LABEL: fmaxnum32_zero_intrinsic:
; ARMV8: @ %bb.0:
; ARMV8-NEXT: vldr s0, .LCPI5_0
@@ -215,6 +268,14 @@ define float @fmaxnum32_non_zero_intrinsic(float %x) {
; ARMV7-NEXT: vmov r0, s0
; ARMV7-NEXT: bx lr
;
+; ARMV7-FP-LABEL: fmaxnum32_non_zero_intrinsic:
+; ARMV7-FP: @ %bb.0:
+; ARMV7-FP-NEXT: vmov.f32 s0, #1.000000e+00
+; ARMV7-FP-NEXT: vmov s2, r0
+; ARMV7-FP-NEXT: vmaxnm.f32 s0, s2, s0
+; ARMV7-FP-NEXT: vmov r0, s0
+; ARMV7-FP-NEXT: bx lr
+;
; ARMV8-LABEL: fmaxnum32_non_zero_intrinsic:
; ARMV8: @ %bb.0:
; ARMV8-NEXT: vmov.f32 s0, #1.000000e+00
@@ -245,6 +306,14 @@ define double @fminnum64_intrinsic(double %x, double %y) {
; ARMV7-NEXT: vmov r0, r1, d16
; ARMV7-NEXT: bx lr
;
+; ARMV7-FP-LABEL: fminnum64_intrinsic:
+; ARMV7-FP: @ %bb.0:
+; ARMV7-FP-NEXT: vmov d16, r2, r3
+; ARMV7-FP-NEXT: vmov d17, r0, r1
+; ARMV7-FP-NEXT: vminnm.f64 d16, d17, d16
+; ARMV7-FP-NEXT: vmov r0, r1, d16
+; ARMV7-FP-NEXT: bx lr
+;
; ARMV8-LABEL: fminnum64_intrinsic:
; ARMV8: @ %bb.0:
; ARMV8-NEXT: vmov d16, r2, r3
@@ -275,6 +344,14 @@ define double @fminnum64_nsz_intrinsic(double %x, double %y) {
; ARMV7-NEXT: vmov r0, r1, d16
; ARMV7-NEXT: bx lr
;
+; ARMV7-FP-LABEL: fminnum64_nsz_intrinsic:
+; ARMV7-FP: @ %bb.0:
+; ARMV7-FP-NEXT: vmov d16, r2, r3
+; ARMV7-FP-NEXT: vmov d17, r0, r1
+; ARMV7-FP-NEXT: vminnm.f64 d16, d17, d16
+; ARMV7-FP-NEXT: vmov r0, r1, d16
+; ARMV7-FP-NEXT: bx lr
+;
; ARMV8-LABEL: fminnum64_nsz_intrinsic:
; ARMV8: @ %bb.0:
; ARMV8-NEXT: vmov d16, r2, r3
@@ -310,6 +387,19 @@ define double @fminnum64_zero_intrinsic(double %x) {
; ARMV7-NEXT: .long 0 @ double -0
; ARMV7-NEXT: .long 2147483648
;
+; ARMV7-FP-LABEL: fminnum64_zero_intrinsic:
+; ARMV7-FP: @ %bb.0:
+; ARMV7-FP-NEXT: vldr d16, .LCPI9_0
+; ARMV7-FP-NEXT: vmov d17, r0, r1
+; ARMV7-FP-NEXT: vminnm.f64 d16, d17, d16
+; ARMV7-FP-NEXT: vmov r0, r1, d16
+; ARMV7-FP-NEXT: bx lr
+; ARMV7-FP-NEXT: .p2align 3
+; ARMV7-FP-NEXT: @ %bb.1:
+; ARMV7-FP-NEXT: .LCPI9_0:
+; ARMV7-FP-NEXT: .long 0 @ double -0
+; ARMV7-FP-NEXT: .long 2147483648
+;
; ARMV8-LABEL: fminnum64_zero_intrinsic:
; ARMV8: @ %bb.0:
; ARMV8-NEXT: vldr d16, .LCPI9_0
@@ -350,6 +440,14 @@ define double @fminnum64_non_zero_intrinsic(double %x) {
; ARMV7-NEXT: vmov r0, r1, d16
; ARMV7-NEXT: bx lr
;
+; ARMV7-FP-LABEL: fminnum64_non_zero_intrinsic:
+; ARMV7-FP: @ %bb.0:
+; ARMV7-FP-NEXT: vmov.f64 d16, #-1.000000e+00
+; ARMV7-FP-NEXT: vmov d17, r0, r1
+; ARMV7-FP-NEXT: vminnm.f64 d16, d17, d16
+; ARMV7-FP-NEXT: vmov r0, r1, d16
+; ARMV7-FP-NEXT: bx lr
+;
; ARMV8-LABEL: fminnum64_non_zero_intrinsic:
; ARMV8: @ %bb.0:
; ARMV8-NEXT: vmov.f64 d16, #-1.000000e+00
@@ -380,6 +478,14 @@ define double at fmaxnum64_intrinsic(double %x, double %y) {
; ARMV7-NEXT: vmov r0, r1, d16
; ARMV7-NEXT: bx lr
;
+; ARMV7-FP-LABEL: fmaxnum64_intrinsic:
+; ARMV7-FP: @ %bb.0:
+; ARMV7-FP-NEXT: vmov d16, r2, r3
+; ARMV7-FP-NEXT: vmov d17, r0, r1
+; ARMV7-FP-NEXT: vmaxnm.f64 d16, d17, d16
+; ARMV7-FP-NEXT: vmov r0, r1, d16
+; ARMV7-FP-NEXT: bx lr
+;
; ARMV8-LABEL: fmaxnum64_intrinsic:
; ARMV8: @ %bb.0:
; ARMV8-NEXT: vmov d16, r2, r3
@@ -410,6 +516,14 @@ define double at fmaxnum64_nsz_intrinsic(double %x, double %y) {
; ARMV7-NEXT: vmov r0, r1, d16
; ARMV7-NEXT: bx lr
;
+; ARMV7-FP-LABEL: fmaxnum64_nsz_intrinsic:
+; ARMV7-FP: @ %bb.0:
+; ARMV7-FP-NEXT: vmov d16, r2, r3
+; ARMV7-FP-NEXT: vmov d17, r0, r1
+; ARMV7-FP-NEXT: vmaxnm.f64 d16, d17, d16
+; ARMV7-FP-NEXT: vmov r0, r1, d16
+; ARMV7-FP-NEXT: bx lr
+;
; ARMV8-LABEL: fmaxnum64_nsz_intrinsic:
; ARMV8: @ %bb.0:
; ARMV8-NEXT: vmov d16, r2, r3
@@ -440,6 +554,14 @@ define double @fmaxnum64_zero_intrinsic(double %x) {
; ARMV7-NEXT: vmov r0, r1, d16
; ARMV7-NEXT: bx lr
;
+; ARMV7-FP-LABEL: fmaxnum64_zero_intrinsic:
+; ARMV7-FP: @ %bb.0:
+; ARMV7-FP-NEXT: vmov.i32 d16, #0x0
+; ARMV7-FP-NEXT: vmov d17, r0, r1
+; ARMV7-FP-NEXT: vmaxnm.f64 d16, d17, d16
+; ARMV7-FP-NEXT: vmov r0, r1, d16
+; ARMV7-FP-NEXT: bx lr
+;
; ARMV8-LABEL: fmaxnum64_zero_intrinsic:
; ARMV8: @ %bb.0:
; ARMV8-NEXT: vldr d16, .LCPI13_0
@@ -480,6 +602,14 @@ define double @fmaxnum64_non_zero_intrinsic(double %x) {
; ARMV7-NEXT: vmov r0, r1, d16
; ARMV7-NEXT: bx lr
;
+; ARMV7-FP-LABEL: fmaxnum64_non_zero_intrinsic:
+; ARMV7-FP: @ %bb.0:
+; ARMV7-FP-NEXT: vmov.f64 d16, #1.000000e+00
+; ARMV7-FP-NEXT: vmov d17, r0, r1
+; ARMV7-FP-NEXT: vmaxnm.f64 d16, d17, d16
+; ARMV7-FP-NEXT: vmov r0, r1, d16
+; ARMV7-FP-NEXT: bx lr
+;
; ARMV8-LABEL: fmaxnum64_non_zero_intrinsic:
; ARMV8: @ %bb.0:
; ARMV8-NEXT: vmov.f64 d16, #1.000000e+00
@@ -522,6 +652,17 @@ define <4 x float> @fminnumv432_intrinsic(<4 x float> %x, <4 x float> %y) {
; ARMV7-NEXT: vmov r0, r1, d0
; ARMV7-NEXT: bx lr
;
+; ARMV7-FP-LABEL: fminnumv432_intrinsic:
+; ARMV7-FP: @ %bb.0:
+; ARMV7-FP-NEXT: vmov d17, r2, r3
+; ARMV7-FP-NEXT: vmov d16, r0, r1
+; ARMV7-FP-NEXT: mov r0, sp
+; ARMV7-FP-NEXT: vld1.64 {d18, d19}, [r0]
+; ARMV7-FP-NEXT: vminnm.f32 q8, q8, q9
+; ARMV7-FP-NEXT: vmov r0, r1, d16
+; ARMV7-FP-NEXT: vmov r2, r3, d17
+; ARMV7-FP-NEXT: bx lr
+;
; ARMV8-LABEL: fminnumv432_intrinsic:
; ARMV8: @ %bb.0:
; ARMV8-NEXT: vldr s0, [sp, #4]
@@ -568,6 +709,17 @@ define <4 x float> @fminnumv432_nsz_intrinsic(<4 x float> %x, <4 x float> %y) {
; ARMV7-NEXT: vmov r2, r3, d17
; ARMV7-NEXT: bx lr
;
+; ARMV7-FP-LABEL: fminnumv432_nsz_intrinsic:
+; ARMV7-FP: @ %bb.0:
+; ARMV7-FP-NEXT: vmov d17, r2, r3
+; ARMV7-FP-NEXT: vmov d16, r0, r1
+; ARMV7-FP-NEXT: mov r0, sp
+; ARMV7-FP-NEXT: vld1.64 {d18, d19}, [r0]
+; ARMV7-FP-NEXT: vminnm.f32 q8, q8, q9
+; ARMV7-FP-NEXT: vmov r0, r1, d16
+; ARMV7-FP-NEXT: vmov r2, r3, d17
+; ARMV7-FP-NEXT: bx lr
+;
; ARMV8-LABEL: fminnumv432_nsz_intrinsic:
; ARMV8: @ %bb.0:
; ARMV8-NEXT: vldr s0, [sp, #4]
@@ -613,6 +765,16 @@ define <4 x float> @fminnumv432_non_zero_intrinsic(<4 x float> %x) {
; ARMV7-NEXT: vmov r2, r3, d17
; ARMV7-NEXT: bx lr
;
+; ARMV7-FP-LABEL: fminnumv432_non_zero_intrinsic:
+; ARMV7-FP: @ %bb.0:
+; ARMV7-FP-NEXT: vmov d17, r2, r3
+; ARMV7-FP-NEXT: vmov d16, r0, r1
+; ARMV7-FP-NEXT: vmov.f32 q9, #-1.000000e+00
+; ARMV7-FP-NEXT: vminnm.f32 q8, q8, q9
+; ARMV7-FP-NEXT: vmov r0, r1, d16
+; ARMV7-FP-NEXT: vmov r2, r3, d17
+; ARMV7-FP-NEXT: bx lr
+;
; ARMV8-LABEL: fminnumv432_non_zero_intrinsic:
; ARMV8: @ %bb.0:
; ARMV8-NEXT: vmov.f32 s0, #-1.000000e+00
@@ -672,6 +834,24 @@ define <4 x float> @fminnumv432_one_zero_intrinsic(<4 x float> %x) {
; ARMV7-NEXT: .LCPI18_0:
; ARMV7-NEXT: .long 0x00000000 @ float 0
;
+; ARMV7-FP-LABEL: fminnumv432_one_zero_intrinsic:
+; ARMV7-FP: @ %bb.0:
+; ARMV7-FP-NEXT: vmov d17, r2, r3
+; ARMV7-FP-NEXT: vmov d16, r0, r1
+; ARMV7-FP-NEXT: adr r0, .LCPI18_0
+; ARMV7-FP-NEXT: vld1.64 {d18, d19}, [r0:128]
+; ARMV7-FP-NEXT: vminnm.f32 q8, q8, q9
+; ARMV7-FP-NEXT: vmov r0, r1, d16
+; ARMV7-FP-NEXT: vmov r2, r3, d17
+; ARMV7-FP-NEXT: bx lr
+; ARMV7-FP-NEXT: .p2align 4
+; ARMV7-FP-NEXT: @ %bb.1:
+; ARMV7-FP-NEXT: .LCPI18_0:
+; ARMV7-FP-NEXT: .long 0xbf800000 @ float -1
+; ARMV7-FP-NEXT: .long 0x00000000 @ float 0
+; ARMV7-FP-NEXT: .long 0xbf800000 @ float -1
+; ARMV7-FP-NEXT: .long 0xbf800000 @ float -1
+;
; ARMV8-LABEL: fminnumv432_one_zero_intrinsic:
; ARMV8: @ %bb.0:
; ARMV8-NEXT: vldr s0, .LCPI18_0
@@ -738,6 +918,17 @@ define <4 x float> @fmaxnumv432_intrinsic(<4 x float> %x, <4 x float> %y) {
; ARMV7-NEXT: vmov r0, r1, d0
; ARMV7-NEXT: bx lr
;
+; ARMV7-FP-LABEL: fmaxnumv432_intrinsic:
+; ARMV7-FP: @ %bb.0:
+; ARMV7-FP-NEXT: vmov d17, r2, r3
+; ARMV7-FP-NEXT: vmov d16, r0, r1
+; ARMV7-FP-NEXT: mov r0, sp
+; ARMV7-FP-NEXT: vld1.64 {d18, d19}, [r0]
+; ARMV7-FP-NEXT: vmaxnm.f32 q8, q8, q9
+; ARMV7-FP-NEXT: vmov r0, r1, d16
+; ARMV7-FP-NEXT: vmov r2, r3, d17
+; ARMV7-FP-NEXT: bx lr
+;
; ARMV8-LABEL: fmaxnumv432_intrinsic:
; ARMV8: @ %bb.0:
; ARMV8-NEXT: vldr s0, [sp, #4]
@@ -784,6 +975,17 @@ define <4 x float> @fmaxnumv432_nsz_intrinsic(<4 x float> %x, <4 x float> %y) {
; ARMV7-NEXT: vmov r2, r3, d17
; ARMV7-NEXT: bx lr
;
+; ARMV7-FP-LABEL: fmaxnumv432_nsz_intrinsic:
+; ARMV7-FP: @ %bb.0:
+; ARMV7-FP-NEXT: vmov d17, r2, r3
+; ARMV7-FP-NEXT: vmov d16, r0, r1
+; ARMV7-FP-NEXT: mov r0, sp
+; ARMV7-FP-NEXT: vld1.64 {d18, d19}, [r0]
+; ARMV7-FP-NEXT: vmaxnm.f32 q8, q8, q9
+; ARMV7-FP-NEXT: vmov r0, r1, d16
+; ARMV7-FP-NEXT: vmov r2, r3, d17
+; ARMV7-FP-NEXT: bx lr
+;
; ARMV8-LABEL: fmaxnumv432_nsz_intrinsic:
; ARMV8: @ %bb.0:
; ARMV8-NEXT: vldr s0, [sp, #4]
@@ -847,6 +1049,16 @@ define <4 x float> @fmaxnumv432_zero_intrinsic(<4 x float> %x) {
; ARMV7-NEXT: .LCPI21_0:
; ARMV7-NEXT: .long 0x00000000 @ float 0
;
+; ARMV7-FP-LABEL: fmaxnumv432_zero_intrinsic:
+; ARMV7-FP: @ %bb.0:
+; ARMV7-FP-NEXT: vmov d17, r2, r3
+; ARMV7-FP-NEXT: vmov d16, r0, r1
+; ARMV7-FP-NEXT: vmov.i32 q9, #0x0
+; ARMV7-FP-NEXT: vmaxnm.f32 q8, q8, q9
+; ARMV7-FP-NEXT: vmov r0, r1, d16
+; ARMV7-FP-NEXT: vmov r2, r3, d17
+; ARMV7-FP-NEXT: bx lr
+;
; ARMV8-LABEL: fmaxnumv432_zero_intrinsic:
; ARMV8: @ %bb.0:
; ARMV8-NEXT: vldr s0, .LCPI21_0
@@ -910,6 +1122,16 @@ define <4 x float> @fmaxnumv432_minus_zero_intrinsic(<4 x float> %x) {
; ARMV7-NEXT: .LCPI22_0:
; ARMV7-NEXT: .long 0x80000000 @ float -0
;
+; ARMV7-FP-LABEL: fmaxnumv432_minus_zero_intrinsic:
+; ARMV7-FP: @ %bb.0:
+; ARMV7-FP-NEXT: vmov d17, r2, r3
+; ARMV7-FP-NEXT: vmov d16, r0, r1
+; ARMV7-FP-NEXT: vmov.i32 q9, #0x80000000
+; ARMV7-FP-NEXT: vmaxnm.f32 q8, q8, q9
+; ARMV7-FP-NEXT: vmov r0, r1, d16
+; ARMV7-FP-NEXT: vmov r2, r3, d17
+; ARMV7-FP-NEXT: bx lr
+;
; ARMV8-LABEL: fmaxnumv432_minus_zero_intrinsic:
; ARMV8: @ %bb.0:
; ARMV8-NEXT: vldr s0, .LCPI22_0
@@ -955,6 +1177,16 @@ define <4 x float> @fmaxnumv432_non_zero_intrinsic(<4 x float> %x) {
; ARMV7-NEXT: vmov r2, r3, d17
; ARMV7-NEXT: bx lr
;
+; ARMV7-FP-LABEL: fmaxnumv432_non_zero_intrinsic:
+; ARMV7-FP: @ %bb.0:
+; ARMV7-FP-NEXT: vmov d17, r2, r3
+; ARMV7-FP-NEXT: vmov d16, r0, r1
+; ARMV7-FP-NEXT: vmov.f32 q9, #1.000000e+00
+; ARMV7-FP-NEXT: vmaxnm.f32 q8, q8, q9
+; ARMV7-FP-NEXT: vmov r0, r1, d16
+; ARMV7-FP-NEXT: vmov r2, r3, d17
+; ARMV7-FP-NEXT: bx lr
+;
; ARMV8-LABEL: fmaxnumv432_non_zero_intrinsic:
; ARMV8: @ %bb.0:
; ARMV8-NEXT: vmov.f32 s0, #1.000000e+00
@@ -1002,6 +1234,22 @@ define <2 x double> @fminnumv264_intrinsic(<2 x double> %x, <2 x double> %y) {
; ARMV7-NEXT: vmov r2, r3, d17
; ARMV7-NEXT: bx lr
;
+; ARMV7-FP-LABEL: fminnumv264_intrinsic:
+; ARMV7-FP: @ %bb.0:
+; ARMV7-FP-NEXT: mov r12, sp
+; ARMV7-FP-NEXT: vld1.64 {d16, d17}, [r12]
+; ARMV7-FP-NEXT: vmov d18, r0, r1
+; ARMV7-FP-NEXT: vmov d19, r2, r3
+; ARMV7-FP-NEXT: vcmp.f64 d16, d18
+; ARMV7-FP-NEXT: vmrs APSR_nzcv, fpscr
+; ARMV7-FP-NEXT: vcmp.f64 d17, d19
+; ARMV7-FP-NEXT: vselgt.f64 d18, d18, d16
+; ARMV7-FP-NEXT: vmrs APSR_nzcv, fpscr
+; ARMV7-FP-NEXT: vmov r0, r1, d18
+; ARMV7-FP-NEXT: vselgt.f64 d16, d19, d17
+; ARMV7-FP-NEXT: vmov r2, r3, d16
+; ARMV7-FP-NEXT: bx lr
+;
; ARMV8-LABEL: fminnumv264_intrinsic:
; ARMV8: @ %bb.0:
; ARMV8-NEXT: vldr d16, [sp, #8]
@@ -1050,6 +1298,22 @@ define <2 x double> @fminnumv264_nsz_intrinsic(<2 x double> %x, <2 x double> %y)
; ARMV7-NEXT: vmov r2, r3, d17
; ARMV7-NEXT: bx lr
;
+; ARMV7-FP-LABEL: fminnumv264_nsz_intrinsic:
+; ARMV7-FP: @ %bb.0:
+; ARMV7-FP-NEXT: mov r12, sp
+; ARMV7-FP-NEXT: vld1.64 {d16, d17}, [r12]
+; ARMV7-FP-NEXT: vmov d18, r0, r1
+; ARMV7-FP-NEXT: vmov d19, r2, r3
+; ARMV7-FP-NEXT: vcmp.f64 d16, d18
+; ARMV7-FP-NEXT: vmrs APSR_nzcv, fpscr
+; ARMV7-FP-NEXT: vcmp.f64 d17, d19
+; ARMV7-FP-NEXT: vselgt.f64 d18, d18, d16
+; ARMV7-FP-NEXT: vmrs APSR_nzcv, fpscr
+; ARMV7-FP-NEXT: vmov r0, r1, d18
+; ARMV7-FP-NEXT: vselgt.f64 d16, d19, d17
+; ARMV7-FP-NEXT: vmov r2, r3, d16
+; ARMV7-FP-NEXT: bx lr
+;
; ARMV8-LABEL: fminnumv264_nsz_intrinsic:
; ARMV8: @ %bb.0:
; ARMV8-NEXT: vldr d16, [sp, #8]
@@ -1098,6 +1362,21 @@ define <2 x double> @fminnumv264_non_zero_intrinsic(<2 x double> %x) {
; ARMV7-NEXT: vmov r2, r3, d16
; ARMV7-NEXT: bx lr
;
+; ARMV7-FP-LABEL: fminnumv264_non_zero_intrinsic:
+; ARMV7-FP: @ %bb.0:
+; ARMV7-FP-NEXT: vmov d17, r0, r1
+; ARMV7-FP-NEXT: vmov.f64 d16, #1.000000e+00
+; ARMV7-FP-NEXT: vcmp.f64 d16, d17
+; ARMV7-FP-NEXT: vmrs APSR_nzcv, fpscr
+; ARMV7-FP-NEXT: vmov d18, r2, r3
+; ARMV7-FP-NEXT: vcmp.f64 d16, d18
+; ARMV7-FP-NEXT: vselgt.f64 d17, d17, d16
+; ARMV7-FP-NEXT: vmrs APSR_nzcv, fpscr
+; ARMV7-FP-NEXT: vmov r0, r1, d17
+; ARMV7-FP-NEXT: vselgt.f64 d16, d18, d16
+; ARMV7-FP-NEXT: vmov r2, r3, d16
+; ARMV7-FP-NEXT: bx lr
+;
; ARMV8-LABEL: fminnumv264_non_zero_intrinsic:
; ARMV8: @ %bb.0:
; ARMV8-NEXT: vmov.f64 d16, #1.000000e+00
@@ -1144,6 +1423,22 @@ define <2 x double> @fminnumv264_one_zero_intrinsic(<2 x double> %x) {
; ARMV7-NEXT: vmov r0, r1, d16
; ARMV7-NEXT: bx lr
;
+; ARMV7-FP-LABEL: fminnumv264_one_zero_intrinsic:
+; ARMV7-FP: @ %bb.0:
+; ARMV7-FP-NEXT: vmov d19, r2, r3
+; ARMV7-FP-NEXT: vcmp.f64 d19, #0
+; ARMV7-FP-NEXT: vmrs APSR_nzcv, fpscr
+; ARMV7-FP-NEXT: vmov d18, r0, r1
+; ARMV7-FP-NEXT: vmov.f64 d16, #-1.000000e+00
+; ARMV7-FP-NEXT: vcmp.f64 d16, d18
+; ARMV7-FP-NEXT: vmov.i32 d17, #0x0
+; ARMV7-FP-NEXT: vmovlt.f64 d17, d19
+; ARMV7-FP-NEXT: vmrs APSR_nzcv, fpscr
+; ARMV7-FP-NEXT: vmov r2, r3, d17
+; ARMV7-FP-NEXT: vselgt.f64 d16, d18, d16
+; ARMV7-FP-NEXT: vmov r0, r1, d16
+; ARMV7-FP-NEXT: bx lr
+;
; ARMV8-LABEL: fminnumv264_one_zero_intrinsic:
; ARMV8: @ %bb.0:
; ARMV8-NEXT: vmov.f64 d16, #-1.000000e+00
@@ -1202,6 +1497,22 @@ define <2 x double> @fmaxnumv264_intrinsic(<2 x double> %x, <2 x double> %y) {
; ARMV7-NEXT: vmov r2, r3, d17
; ARMV7-NEXT: bx lr
;
+; ARMV7-FP-LABEL: fmaxnumv264_intrinsic:
+; ARMV7-FP: @ %bb.0:
+; ARMV7-FP-NEXT: mov r12, sp
+; ARMV7-FP-NEXT: vld1.64 {d16, d17}, [r12]
+; ARMV7-FP-NEXT: vmov d18, r0, r1
+; ARMV7-FP-NEXT: vcmp.f64 d18, d16
+; ARMV7-FP-NEXT: vmrs APSR_nzcv, fpscr
+; ARMV7-FP-NEXT: vmov d19, r2, r3
+; ARMV7-FP-NEXT: vcmp.f64 d19, d17
+; ARMV7-FP-NEXT: vselgt.f64 d18, d18, d16
+; ARMV7-FP-NEXT: vmrs APSR_nzcv, fpscr
+; ARMV7-FP-NEXT: vmov r0, r1, d18
+; ARMV7-FP-NEXT: vselgt.f64 d16, d19, d17
+; ARMV7-FP-NEXT: vmov r2, r3, d16
+; ARMV7-FP-NEXT: bx lr
+;
; ARMV8-LABEL: fmaxnumv264_intrinsic:
; ARMV8: @ %bb.0:
; ARMV8-NEXT: vldr d16, [sp, #8]
@@ -1250,6 +1561,22 @@ define <2 x double> @fmaxnumv264_nsz_intrinsic(<2 x double> %x, <2 x double> %y)
; ARMV7-NEXT: vmov r2, r3, d17
; ARMV7-NEXT: bx lr
;
+; ARMV7-FP-LABEL: fmaxnumv264_nsz_intrinsic:
+; ARMV7-FP: @ %bb.0:
+; ARMV7-FP-NEXT: mov r12, sp
+; ARMV7-FP-NEXT: vld1.64 {d16, d17}, [r12]
+; ARMV7-FP-NEXT: vmov d18, r0, r1
+; ARMV7-FP-NEXT: vcmp.f64 d18, d16
+; ARMV7-FP-NEXT: vmrs APSR_nzcv, fpscr
+; ARMV7-FP-NEXT: vmov d19, r2, r3
+; ARMV7-FP-NEXT: vcmp.f64 d19, d17
+; ARMV7-FP-NEXT: vselgt.f64 d18, d18, d16
+; ARMV7-FP-NEXT: vmrs APSR_nzcv, fpscr
+; ARMV7-FP-NEXT: vmov r0, r1, d18
+; ARMV7-FP-NEXT: vselgt.f64 d16, d19, d17
+; ARMV7-FP-NEXT: vmov r2, r3, d16
+; ARMV7-FP-NEXT: bx lr
+;
; ARMV8-LABEL: fmaxnumv264_nsz_intrinsic:
; ARMV8: @ %bb.0:
; ARMV8-NEXT: vldr d16, [sp, #8]
@@ -1303,6 +1630,27 @@ define <2 x double> @fmaxnumv264_zero_intrinsic(<2 x double> %x) {
; ARMV7-NEXT: .long 0 @ double -0
; ARMV7-NEXT: .long 2147483648
;
+; ARMV7-FP-LABEL: fmaxnumv264_zero_intrinsic:
+; ARMV7-FP: @ %bb.0:
+; ARMV7-FP-NEXT: vmov d18, r0, r1
+; ARMV7-FP-NEXT: vldr d16, .LCPI30_0
+; ARMV7-FP-NEXT: vcmp.f64 d18, #0
+; ARMV7-FP-NEXT: vmrs APSR_nzcv, fpscr
+; ARMV7-FP-NEXT: vmov d19, r2, r3
+; ARMV7-FP-NEXT: vcmp.f64 d19, d16
+; ARMV7-FP-NEXT: vmov.i32 d17, #0x0
+; ARMV7-FP-NEXT: vselgt.f64 d17, d18, d17
+; ARMV7-FP-NEXT: vmrs APSR_nzcv, fpscr
+; ARMV7-FP-NEXT: vmov r0, r1, d17
+; ARMV7-FP-NEXT: vselgt.f64 d16, d19, d16
+; ARMV7-FP-NEXT: vmov r2, r3, d16
+; ARMV7-FP-NEXT: bx lr
+; ARMV7-FP-NEXT: .p2align 3
+; ARMV7-FP-NEXT: @ %bb.1:
+; ARMV7-FP-NEXT: .LCPI30_0:
+; ARMV7-FP-NEXT: .long 0 @ double -0
+; ARMV7-FP-NEXT: .long 2147483648
+;
; ARMV8-LABEL: fmaxnumv264_zero_intrinsic:
; ARMV8: @ %bb.0:
; ARMV8-NEXT: vldr d16, .LCPI30_0
@@ -1372,6 +1720,26 @@ define <2 x double> @fmaxnumv264_minus_zero_intrinsic(<2 x double> %x) {
; ARMV7-NEXT: .long 0 @ double -0
; ARMV7-NEXT: .long 2147483648
;
+; ARMV7-FP-LABEL: fmaxnumv264_minus_zero_intrinsic:
+; ARMV7-FP: @ %bb.0:
+; ARMV7-FP-NEXT: vldr d16, .LCPI31_0
+; ARMV7-FP-NEXT: vmov d17, r0, r1
+; ARMV7-FP-NEXT: vmov d18, r2, r3
+; ARMV7-FP-NEXT: vcmp.f64 d17, d16
+; ARMV7-FP-NEXT: vmrs APSR_nzcv, fpscr
+; ARMV7-FP-NEXT: vcmp.f64 d18, d16
+; ARMV7-FP-NEXT: vselgt.f64 d17, d17, d16
+; ARMV7-FP-NEXT: vmrs APSR_nzcv, fpscr
+; ARMV7-FP-NEXT: vmov r0, r1, d17
+; ARMV7-FP-NEXT: vselgt.f64 d16, d18, d16
+; ARMV7-FP-NEXT: vmov r2, r3, d16
+; ARMV7-FP-NEXT: bx lr
+; ARMV7-FP-NEXT: .p2align 3
+; ARMV7-FP-NEXT: @ %bb.1:
+; ARMV7-FP-NEXT: .LCPI31_0:
+; ARMV7-FP-NEXT: .long 0 @ double -0
+; ARMV7-FP-NEXT: .long 2147483648
+;
; ARMV8-LABEL: fmaxnumv264_minus_zero_intrinsic:
; ARMV8: @ %bb.0:
; ARMV8-NEXT: vldr d16, .LCPI31_0
@@ -1428,6 +1796,21 @@ define <2 x double> @fmaxnumv264_non_zero_intrinsic(<2 x double> %x) {
; ARMV7-NEXT: vmov r2, r3, d16
; ARMV7-NEXT: bx lr
;
+; ARMV7-FP-LABEL: fmaxnumv264_non_zero_intrinsic:
+; ARMV7-FP: @ %bb.0:
+; ARMV7-FP-NEXT: vmov.f64 d16, #1.000000e+00
+; ARMV7-FP-NEXT: vmov d17, r0, r1
+; ARMV7-FP-NEXT: vcmp.f64 d17, d16
+; ARMV7-FP-NEXT: vmrs APSR_nzcv, fpscr
+; ARMV7-FP-NEXT: vmov d18, r2, r3
+; ARMV7-FP-NEXT: vcmp.f64 d18, d16
+; ARMV7-FP-NEXT: vselgt.f64 d17, d17, d16
+; ARMV7-FP-NEXT: vmrs APSR_nzcv, fpscr
+; ARMV7-FP-NEXT: vmov r0, r1, d17
+; ARMV7-FP-NEXT: vselgt.f64 d16, d18, d16
+; ARMV7-FP-NEXT: vmov r2, r3, d16
+; ARMV7-FP-NEXT: bx lr
+;
; ARMV8-LABEL: fmaxnumv264_non_zero_intrinsic:
; ARMV8: @ %bb.0:
; ARMV8-NEXT: vmov.f64 d16, #1.000000e+00
@@ -1467,6 +1850,15 @@ define void @pr65820(ptr %y, <4 x float> %splat) {
; ARMV7-NEXT: vst1.32 {d16, d17}, [r0]
; ARMV7-NEXT: bx lr
;
+; ARMV7-FP-LABEL: pr65820:
+; ARMV7-FP: @ %bb.0: @ %entry
+; ARMV7-FP-NEXT: vmov d16, r2, r3
+; ARMV7-FP-NEXT: vmov.i32 q9, #0x0
+; ARMV7-FP-NEXT: vdup.32 q8, d16[0]
+; ARMV7-FP-NEXT: vmaxnm.f32 q8, q8, q9
+; ARMV7-FP-NEXT: vst1.32 {d16, d17}, [r0]
+; ARMV7-FP-NEXT: bx lr
+;
; ARMV8-LABEL: pr65820:
; ARMV8: @ %bb.0: @ %entry
; ARMV8-NEXT: vldr s0, .LCPI33_0
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