[llvm] [InlineAsm] wrap ConstraintCode in enum class NFC (PR #66003)

via llvm-commits llvm-commits at lists.llvm.org
Mon Sep 11 13:03:56 PDT 2023


llvmbot wrote:

@llvm/pr-subscribers-backend-m68k

<details>
<summary>Changes</summary>

Similar to
commit 2fad6e69851e ("[InlineAsm] wrap Kind in enum class NFC")

Fix the TODOs added in
commit 93bd428742f9 ("[InlineAsm] refactor InlineAsm class NFC (#65649)")

--

Patch is 34.89 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/66003.diff

25 Files Affected:

- (modified) llvm/include/llvm/CodeGen/SelectionDAGISel.h (+4-3) 
- (modified) llvm/include/llvm/CodeGen/TargetLowering.h (+7-6) 
- (modified) llvm/include/llvm/IR/InlineAsm.h (+77-77) 
- (modified) llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp (+3-3) 
- (modified) llvm/lib/CodeGen/MachineInstr.cpp (+1-1) 
- (modified) llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (+6-6) 
- (modified) llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (+2-1) 
- (modified) llvm/lib/CodeGen/TargetInstrInfo.cpp (+1-1) 
- (modified) llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp (+9-7) 
- (modified) llvm/lib/Target/AArch64/AArch64ISelLowering.h (+3-2) 
- (modified) llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp (+17-16) 
- (modified) llvm/lib/Target/ARM/ARMISelLowering.h (+10-10) 
- (modified) llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp (+6-4) 
- (modified) llvm/lib/Target/AVR/AVRISelLowering.cpp (+2-2) 
- (modified) llvm/lib/Target/AVR/AVRISelLowering.h (+2-1) 
- (modified) llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp (+7-4) 
- (modified) llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp (+9-6) 
- (modified) llvm/lib/Target/M68k/M68kISelLowering.cpp (+5-4) 
- (modified) llvm/lib/Target/M68k/M68kISelLowering.h (+2-1) 
- (modified) llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp (+5-4) 
- (modified) llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h (+4-2) 
- (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+2-2) 
- (modified) llvm/lib/Target/RISCV/RISCVISelLowering.h (+2-1) 
- (modified) llvm/lib/Target/X86/X86ISelDAGToDAG.cpp (+12-11) 
- (modified) llvm/lib/Target/X86/X86ISelLowering.h (+2-2) 


<pre>
diff --git a/llvm/include/llvm/CodeGen/SelectionDAGISel.h b/llvm/include/llvm/CodeGen/SelectionDAGISel.h
index 557c6ef03d96b98..d3907865a659121 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAGISel.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAGISel.h
@@ -89,9 +89,10 @@ class SelectionDAGISel : public MachineFunctionPass {
   /// not match or is not implemented, return true.  The resultant operands
   /// (which will appear in the machine instruction) should be added to the
   /// OutOps vector.
-  virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
-                                            unsigned ConstraintID,
-                                            std::vector<SDValue> &OutOps) {
+  virtual bool
+  SelectInlineAsmMemoryOperand(const SDValue &Op,
+                               const InlineAsm::ConstraintCode ConstraintID,
+                               std::vector<SDValue> &OutOps) {
     return true;
   }
 
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
index 12b280d5b1a0bcd..f4feab495932294 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -4833,16 +4833,17 @@ class TargetLowering : public TargetLoweringBase {
   getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
                                StringRef Constraint, MVT VT) const;
 
-  virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const {
+  virtual InlineAsm::ConstraintCode
+  getInlineAsmMemConstraint(StringRef ConstraintCode) const {
     if (ConstraintCode == "m")
-      return InlineAsm::Constraint_m;
+      return InlineAsm::ConstraintCode::m;
     if (ConstraintCode == "o")
-      return InlineAsm::Constraint_o;
+      return InlineAsm::ConstraintCode::o;
     if (ConstraintCode == "X")
-      return InlineAsm::Constraint_X;
+      return InlineAsm::ConstraintCode::X;
     if (ConstraintCode == "p")
-      return InlineAsm::Constraint_p;
-    return InlineAsm::Constraint_Unknown;
+      return InlineAsm::ConstraintCode::p;
+    return InlineAsm::ConstraintCode::Unknown;
   }
 
   /// Try to replace an X constraint, which matches anything, with another that
diff --git a/llvm/include/llvm/IR/InlineAsm.h b/llvm/include/llvm/IR/InlineAsm.h
index f73666fa8dc08e7..a4032ce7abde331 100644
--- a/llvm/include/llvm/IR/InlineAsm.h
+++ b/llvm/include/llvm/IR/InlineAsm.h
@@ -217,48 +217,6 @@ class InlineAsm final : public Value {
     Extra_MayLoad = 8,
     Extra_MayStore = 16,
     Extra_IsConvergent = 32,
-
-    // Memory constraint codes.
-    // These could be tablegenerated but there's little need to do that since
-    // there's plenty of space in the encoding to support the union of all
-    // constraint codes for all targets.
-    // Addresses are included here as they need to be treated the same by the
-    // backend, the only difference is that they are not used to actaully
-    // access memory by the instruction.
-    // TODO: convert to enum?
-    Constraint_Unknown = 0,
-    Constraint_es,
-    Constraint_i,
-    Constraint_k,
-    Constraint_m,
-    Constraint_o,
-    Constraint_v,
-    Constraint_A,
-    Constraint_Q,
-    Constraint_R,
-    Constraint_S,
-    Constraint_T,
-    Constraint_Um,
-    Constraint_Un,
-    Constraint_Uq,
-    Constraint_Us,
-    Constraint_Ut,
-    Constraint_Uv,
-    Constraint_Uy,
-    Constraint_X,
-    Constraint_Z,
-    Constraint_ZB,
-    Constraint_ZC,
-    Constraint_Zy,
-
-    // Address constraints
-    Constraint_p,
-    Constraint_ZQ,
-    Constraint_ZR,
-    Constraint_ZS,
-    Constraint_ZT,
-
-    Constraints_Max = Constraint_ZT,
   };
 
   // Inline asm operands map to multiple SDNode / MachineInstr operands.
@@ -274,6 +232,46 @@ class InlineAsm final : public Value {
     Func = 7,               // Address operand of function call
   };
 
+  // Memory constraint codes.
+  // Addresses are included here as they need to be treated the same by the
+  // backend, the only difference is that they are not used to actaully
+  // access memory by the instruction.
+  enum class ConstraintCode : uint32_t {
+    Unknown = 0,
+    es,
+    i,
+    k,
+    m,
+    o,
+    v,
+    A,
+    Q,
+    R,
+    S,
+    T,
+    Um,
+    Un,
+    Uq,
+    Us,
+    Ut,
+    Uv,
+    Uy,
+    X,
+    Z,
+    ZB,
+    ZC,
+    Zy,
+
+    // Address constraints
+    p,
+    ZQ,
+    ZR,
+    ZS,
+    ZT,
+
+    Max = ZT,
+  };
+
   // These are helper methods for dealing with flags in the INLINEASM SDNode
   // in the backend.
   //
@@ -375,11 +373,14 @@ class InlineAsm final : public Value {
       return true;
     }
 
-    // TODO: convert to enum?
-    unsigned getMemoryConstraintID() const {
+    ConstraintCode getMemoryConstraintID() const {
       assert((isMemKind() || isFuncKind()) &&
              "Not expected mem or function flag!");
-      return getData();
+      uint32_t D = getData();
+      assert(D < static_cast<uint32_t>(ConstraintCode::Max) &&
+             D >= static_cast<uint32_t>(ConstraintCode::Unknown) &&
+             "unexpected value for memory constraint");
+      return static_cast<ConstraintCode>(D);
     }
 
     /// setMatchingOp - Augment an existing flag with information indicating
@@ -403,12 +404,11 @@ class InlineAsm final : public Value {
 
     /// setMemConstraint - Augment an existing flag with the constraint code for
     /// a memory constraint.
-    void setMemConstraint(unsigned Constraint) {
+    void setMemConstraint(ConstraintCode C) {
       assert((isMemKind() || isFuncKind()) &&
              "Flag is not a memory or function constraint!");
-      assert(Constraint <= Constraints_Max && "Unknown constraint ID");
       assert(getData() == 0 && "Mem constraint already set");
-      setData(Constraint);
+      setData(static_cast<uint32_t>(C));
     }
     /// clearMemConstraint - Similar to setMemConstraint(0), but without the
     /// assertion checking that the constraint has not been set previously.
@@ -443,61 +443,61 @@ class InlineAsm final : public Value {
     return Result;
   }
 
-  static StringRef getMemConstraintName(unsigned Constraint) {
-    switch (Constraint) {
-    case InlineAsm::Constraint_es:
+  static StringRef getMemConstraintName(const ConstraintCode C) {
+    switch (C) {
+    case ConstraintCode::es:
       return "es";
-    case InlineAsm::Constraint_i:
+    case ConstraintCode::i:
       return "i";
-    case InlineAsm::Constraint_k:
+    case ConstraintCode::k:
       return "k";
-    case InlineAsm::Constraint_m:
+    case ConstraintCode::m:
       return "m";
-    case InlineAsm::Constraint_o:
+    case ConstraintCode::o:
       return "o";
-    case InlineAsm::Constraint_v:
+    case ConstraintCode::v:
       return "v";
-    case InlineAsm::Constraint_Q:
+    case ConstraintCode::Q:
       return "Q";
-    case InlineAsm::Constraint_R:
+    case ConstraintCode::R:
       return "R";
-    case InlineAsm::Constraint_S:
+    case ConstraintCode::S:
       return "S";
-    case InlineAsm::Constraint_T:
+    case ConstraintCode::T:
       return "T";
-    case InlineAsm::Constraint_Um:
+    case ConstraintCode::Um:
       return "Um";
-    case InlineAsm::Constraint_Un:
+    case ConstraintCode::Un:
       return "Un";
-    case InlineAsm::Constraint_Uq:
+    case ConstraintCode::Uq:
       return "Uq";
-    case InlineAsm::Constraint_Us:
+    case ConstraintCode::Us:
       return "Us";
-    case InlineAsm::Constraint_Ut:
+    case ConstraintCode::Ut:
       return "Ut";
-    case InlineAsm::Constraint_Uv:
+    case ConstraintCode::Uv:
       return "Uv";
-    case InlineAsm::Constraint_Uy:
+    case ConstraintCode::Uy:
       return "Uy";
-    case InlineAsm::Constraint_X:
+    case ConstraintCode::X:
       return "X";
-    case InlineAsm::Constraint_Z:
+    case ConstraintCode::Z:
       return "Z";
-    case InlineAsm::Constraint_ZB:
+    case ConstraintCode::ZB:
       return "ZB";
-    case InlineAsm::Constraint_ZC:
+    case ConstraintCode::ZC:
       return "ZC";
-    case InlineAsm::Constraint_Zy:
+    case ConstraintCode::Zy:
       return "Zy";
-    case InlineAsm::Constraint_p:
+    case ConstraintCode::p:
       return "p";
-    case InlineAsm::Constraint_ZQ:
+    case ConstraintCode::ZQ:
       return "ZQ";
-    case InlineAsm::Constraint_ZR:
+    case ConstraintCode::ZR:
       return "ZR";
-    case InlineAsm::Constraint_ZS:
+    case ConstraintCode::ZS:
       return "ZS";
-    case InlineAsm::Constraint_ZT:
+    case ConstraintCode::ZT:
       return "ZT";
     default:
       llvm_unreachable("Unknown memory constraint");
diff --git a/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp b/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
index 9944ba15997687a..00dba57fcb80227 100644
--- a/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
@@ -373,9 +373,9 @@ bool InlineAsmLowering::lowerInlineAsm(
     switch (OpInfo.Type) {
     case InlineAsm::isOutput:
       if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
-        unsigned ConstraintID =
+        const InlineAsm::ConstraintCode ConstraintID =
             TLI->getInlineAsmMemConstraint(OpInfo.ConstraintCode);
-        assert(ConstraintID != InlineAsm::Constraint_Unknown &&
+        assert(ConstraintID != InlineAsm::ConstraintCode::Unknown &&
                "Failed to convert memory constraint code to constraint id.");
 
         // Add information to the INLINEASM instruction to know about this
@@ -517,7 +517,7 @@ bool InlineAsmLowering::lowerInlineAsm(
 
         assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
 
-        unsigned ConstraintID =
+        const InlineAsm::ConstraintCode ConstraintID =
             TLI->getInlineAsmMemConstraint(OpInfo.ConstraintCode);
         InlineAsm::Flag OpFlags(InlineAsm::Kind::Mem, 1);
         OpFlags.setMemConstraint(ConstraintID);
diff --git a/llvm/lib/CodeGen/MachineInstr.cpp b/llvm/lib/CodeGen/MachineInstr.cpp
index 8cc3391e0d96a3d..d8467e2af8786ec 100644
--- a/llvm/lib/CodeGen/MachineInstr.cpp
+++ b/llvm/lib/CodeGen/MachineInstr.cpp
@@ -1778,7 +1778,7 @@ void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST,
       }
 
       if (F.isMemKind()) {
-        const unsigned MCID = F.getMemoryConstraintID();
+        const InlineAsm::ConstraintCode MCID = F.getMemoryConstraintID();
         OS << ":" << InlineAsm::getMemConstraintName(MCID);
       }
 
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 738dd10633db6a5..720fc4944161225 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -9281,9 +9281,9 @@ void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call,
     switch (OpInfo.Type) {
     case InlineAsm::isOutput:
       if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
-        unsigned ConstraintID =
+        const InlineAsm::ConstraintCode ConstraintID =
             TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
-        assert(ConstraintID != InlineAsm::Constraint_Unknown &&
+        assert(ConstraintID != InlineAsm::ConstraintCode::Unknown &&
                "Failed to convert memory constraint code to constraint id.");
 
         // Add information to the INLINEASM node to know about this output.
@@ -9413,9 +9413,9 @@ void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call,
                    TLI.getPointerTy(DAG.getDataLayout()) &&
                "Memory operands expect pointer values");
 
-        unsigned ConstraintID =
+        const InlineAsm::ConstraintCode ConstraintID =
             TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
-        assert(ConstraintID != InlineAsm::Constraint_Unknown &&
+        assert(ConstraintID != InlineAsm::ConstraintCode::Unknown &&
                "Failed to convert memory constraint code to constraint id.");
 
         // Add information to the INLINEASM node to know about this input.
@@ -9429,9 +9429,9 @@ void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call,
       }
 
       if (OpInfo.ConstraintType == TargetLowering::C_Address) {
-        unsigned ConstraintID =
+        const InlineAsm::ConstraintCode ConstraintID =
             TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
-        assert(ConstraintID != InlineAsm::Constraint_Unknown &&
+        assert(ConstraintID != InlineAsm::ConstraintCode::Unknown &&
                "Failed to convert memory constraint code to constraint id.");
 
         InlineAsm::Flag ResOpType(InlineAsm::Kind::Mem, 1);
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index a7873241df62e52..91b9d77eed70596 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -2101,7 +2101,8 @@ void SelectionDAGISel::SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops,
 
       // Otherwise, this is a memory operand.  Ask the target to select it.
       std::vector<SDValue> SelOps;
-      unsigned ConstraintID = Flags.getMemoryConstraintID();
+      const InlineAsm::ConstraintCode ConstraintID =
+          Flags.getMemoryConstraintID();
       if (SelectInlineAsmMemoryOperand(InOps[i+1], ConstraintID, SelOps))
         report_fatal_error("Could not match memory address.  Inline asm"
                            " failure!");
diff --git a/llvm/lib/CodeGen/TargetInstrInfo.cpp b/llvm/lib/CodeGen/TargetInstrInfo.cpp
index 686044ea572ac0d..bf1605f06bd88d6 100644
--- a/llvm/lib/CodeGen/TargetInstrInfo.cpp
+++ b/llvm/lib/CodeGen/TargetInstrInfo.cpp
@@ -1622,7 +1622,7 @@ std::string TargetInstrInfo::createMIROperandComment(
   }
 
   if (F.isMemKind()) {
-    const unsigned MCID = F.getMemoryConstraintID();
+    InlineAsm::ConstraintCode MCID = F.getMemoryConstraintID();
     OS << ":" << InlineAsm::getMemConstraintName(MCID);
   }
 
diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
index 60a155a86667e89..740995849740fef 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -61,9 +61,10 @@ class AArch64DAGToDAGISel : public SelectionDAGISel {
 
   /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
   /// inline asm expressions.
-  bool SelectInlineAsmMemoryOperand(const SDValue &Op,
-                                    unsigned ConstraintID,
-                                    std::vector<SDValue> &OutOps) override;
+  bool
+  SelectInlineAsmMemoryOperand(const SDValue &Op,
+                               const InlineAsm::ConstraintCode ConstraintID,
+                               std::vector<SDValue> &OutOps) override;
 
   template <signed Low, signed High, signed Scale>
   bool SelectRDVLImm(SDValue N, SDValue &Imm);
@@ -533,13 +534,14 @@ static bool isIntImmediateEq(SDValue N, const uint64_t ImmExpected) {
 #endif
 
 bool AArch64DAGToDAGISel::SelectInlineAsmMemoryOperand(
-    const SDValue &Op, unsigned ConstraintID, std::vector<SDValue> &OutOps) {
+    const SDValue &Op, const InlineAsm::ConstraintCode ConstraintID,
+    std::vector<SDValue> &OutOps) {
   switch(ConstraintID) {
   default:
     llvm_unreachable("Unexpected asm memory constraint");
-  case InlineAsm::Constraint_m:
-  case InlineAsm::Constraint_o:
-  case InlineAsm::Constraint_Q:
+  case InlineAsm::ConstraintCode::m:
+  case InlineAsm::ConstraintCode::o:
+  case InlineAsm::ConstraintCode::Q:
     // We need to make sure that this one operand does not end up in XZR, thus
     // require the address to be in a PointerRegClass register.
     const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
index 67c344318e0d3ec..f2696b6b97593a1 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
@@ -1169,9 +1169,10 @@ class AArch64TargetLowering : public TargetLowering {
                                     std::vector<SDValue> &Ops,
                                     SelectionDAG &DAG) const override;
 
-  unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
+  InlineAsm::ConstraintCode
+  getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
     if (ConstraintCode == "Q")
-      return InlineAsm::Constraint_Q;
+      return InlineAsm::ConstraintCode::Q;
     // FIXME: clang has code for 'Ump', 'Utf', 'Usa', and 'Ush' but these are
     //        followed by llvm_unreachable so we'll leave them unimplemented in
     //        the backend for now.
diff --git a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
index 5f4fab0675824fd..9956b1b040b329d 100644
--- a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -331,8 +331,10 @@ class ARMDAGToDAGISel : public SelectionDAGISel {
 
   /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
   /// inline asm expressions.
-  bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
-                                    std::vector<SDValue> &OutOps) override;
+  bool
+  SelectInlineAsmMemoryOperand(const SDValue &Op,
+                               const InlineAsm::ConstraintCode ConstraintID,
+                               std::vector<SDValue> &OutOps) override;
 
   // Form pairs of consecutive R, S, D, or Q registers.
   SDNode *createGPRPairNode(EVT VT, SDValue V0, SDValue V1);
@@ -5864,23 +5866,22 @@ bool ARMDAGToDAGISel::tryInlineAsm(SDNode *N){
   return true;
 }
 
-
-bool ARMDAGToDAGISel::
-SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
-                             std::vector<SDValue> &OutOps) {
+bool ARMDAGToDAGISel::SelectInlineAsmMemoryOperand(
+    const SDValue &Op, const InlineAsm::ConstraintCode ConstraintID,
+    std::vector<SDValue> &OutOps) {
   switch(ConstraintID) {
   default:
     llvm_unreachable("Unexpected asm memory constraint");
-  case InlineAsm::Constraint_m:
-  case InlineAsm::Constraint_o:
-  case InlineAsm::Constraint_Q:
-  case InlineAsm::Constraint_Um:
-  case InlineAsm::Constraint_Un:
-  case InlineAsm::Constraint_Uq:
-  case InlineAsm::Constraint_Us:
-  case InlineAsm::Constraint_Ut:
-  case InlineAsm::Constraint_Uv:
-  case InlineAsm::Constraint_Uy:
+  case InlineAsm::ConstraintCode::m:
+  case InlineAsm::ConstraintCode::o:
+  case InlineAsm::ConstraintCode::Q:
+  case InlineAsm::ConstraintCode::Um:
+  case InlineAsm::ConstraintCode::Un:
+  case InlineAsm::ConstraintCode::Uq:
+  case InlineAsm::ConstraintCode::Us:
+  case InlineAsm::ConstraintCod...
<truncated>
</pre>

</details>

https://github.com/llvm/llvm-project/pull/66003


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