[llvm] [InlineAsm] wrap ConstraintCode in enum class NFC (PR #66003)
Nick Desaulniers via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 11 13:02:55 PDT 2023
https://github.com/nickdesaulniers created https://github.com/llvm/llvm-project/pull/66003:
Similar to
commit 2fad6e69851e ("[InlineAsm] wrap Kind in enum class NFC")
Fix the TODOs added in
commit 93bd428742f9 ("[InlineAsm] refactor InlineAsm class NFC (#65649)")
>From fe3d91467bc6a02dc6c3d9e31eff2f1ee9434f63 Mon Sep 17 00:00:00 2001
From: Nick Desaulniers <ndesaulniers at google.com>
Date: Mon, 11 Sep 2023 12:48:14 -0700
Subject: [PATCH] [InlineAsm] wrap ConstraintCode in enum class NFC
Similar to
commit 2fad6e69851e ("[InlineAsm] wrap Kind in enum class NFC")
Fix the TODOs added in
commit 93bd428742f9 ("[InlineAsm] refactor InlineAsm class NFC (#65649)")
---
llvm/include/llvm/CodeGen/SelectionDAGISel.h | 7 +-
llvm/include/llvm/CodeGen/TargetLowering.h | 13 +-
llvm/include/llvm/IR/InlineAsm.h | 154 +++++++++---------
.../CodeGen/GlobalISel/InlineAsmLowering.cpp | 6 +-
llvm/lib/CodeGen/MachineInstr.cpp | 2 +-
.../SelectionDAG/SelectionDAGBuilder.cpp | 12 +-
.../CodeGen/SelectionDAG/SelectionDAGISel.cpp | 3 +-
llvm/lib/CodeGen/TargetInstrInfo.cpp | 2 +-
.../Target/AArch64/AArch64ISelDAGToDAG.cpp | 16 +-
llvm/lib/Target/AArch64/AArch64ISelLowering.h | 5 +-
llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp | 33 ++--
llvm/lib/Target/ARM/ARMISelLowering.h | 20 +--
llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp | 10 +-
llvm/lib/Target/AVR/AVRISelLowering.cpp | 4 +-
llvm/lib/Target/AVR/AVRISelLowering.h | 3 +-
llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp | 11 +-
llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp | 15 +-
llvm/lib/Target/M68k/M68kISelLowering.cpp | 9 +-
llvm/lib/Target/M68k/M68kISelLowering.h | 3 +-
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp | 9 +-
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h | 6 +-
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 4 +-
llvm/lib/Target/RISCV/RISCVISelLowering.h | 3 +-
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp | 23 +--
llvm/lib/Target/X86/X86ISelLowering.h | 4 +-
25 files changed, 200 insertions(+), 177 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/SelectionDAGISel.h b/llvm/include/llvm/CodeGen/SelectionDAGISel.h
index 557c6ef03d96b98..d3907865a659121 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAGISel.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAGISel.h
@@ -89,9 +89,10 @@ class SelectionDAGISel : public MachineFunctionPass {
/// not match or is not implemented, return true. The resultant operands
/// (which will appear in the machine instruction) should be added to the
/// OutOps vector.
- virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
- unsigned ConstraintID,
- std::vector<SDValue> &OutOps) {
+ virtual bool
+ SelectInlineAsmMemoryOperand(const SDValue &Op,
+ const InlineAsm::ConstraintCode ConstraintID,
+ std::vector<SDValue> &OutOps) {
return true;
}
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
index 12b280d5b1a0bcd..f4feab495932294 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -4833,16 +4833,17 @@ class TargetLowering : public TargetLoweringBase {
getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
StringRef Constraint, MVT VT) const;
- virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const {
+ virtual InlineAsm::ConstraintCode
+ getInlineAsmMemConstraint(StringRef ConstraintCode) const {
if (ConstraintCode == "m")
- return InlineAsm::Constraint_m;
+ return InlineAsm::ConstraintCode::m;
if (ConstraintCode == "o")
- return InlineAsm::Constraint_o;
+ return InlineAsm::ConstraintCode::o;
if (ConstraintCode == "X")
- return InlineAsm::Constraint_X;
+ return InlineAsm::ConstraintCode::X;
if (ConstraintCode == "p")
- return InlineAsm::Constraint_p;
- return InlineAsm::Constraint_Unknown;
+ return InlineAsm::ConstraintCode::p;
+ return InlineAsm::ConstraintCode::Unknown;
}
/// Try to replace an X constraint, which matches anything, with another that
diff --git a/llvm/include/llvm/IR/InlineAsm.h b/llvm/include/llvm/IR/InlineAsm.h
index f73666fa8dc08e7..a4032ce7abde331 100644
--- a/llvm/include/llvm/IR/InlineAsm.h
+++ b/llvm/include/llvm/IR/InlineAsm.h
@@ -217,48 +217,6 @@ class InlineAsm final : public Value {
Extra_MayLoad = 8,
Extra_MayStore = 16,
Extra_IsConvergent = 32,
-
- // Memory constraint codes.
- // These could be tablegenerated but there's little need to do that since
- // there's plenty of space in the encoding to support the union of all
- // constraint codes for all targets.
- // Addresses are included here as they need to be treated the same by the
- // backend, the only difference is that they are not used to actaully
- // access memory by the instruction.
- // TODO: convert to enum?
- Constraint_Unknown = 0,
- Constraint_es,
- Constraint_i,
- Constraint_k,
- Constraint_m,
- Constraint_o,
- Constraint_v,
- Constraint_A,
- Constraint_Q,
- Constraint_R,
- Constraint_S,
- Constraint_T,
- Constraint_Um,
- Constraint_Un,
- Constraint_Uq,
- Constraint_Us,
- Constraint_Ut,
- Constraint_Uv,
- Constraint_Uy,
- Constraint_X,
- Constraint_Z,
- Constraint_ZB,
- Constraint_ZC,
- Constraint_Zy,
-
- // Address constraints
- Constraint_p,
- Constraint_ZQ,
- Constraint_ZR,
- Constraint_ZS,
- Constraint_ZT,
-
- Constraints_Max = Constraint_ZT,
};
// Inline asm operands map to multiple SDNode / MachineInstr operands.
@@ -274,6 +232,46 @@ class InlineAsm final : public Value {
Func = 7, // Address operand of function call
};
+ // Memory constraint codes.
+ // Addresses are included here as they need to be treated the same by the
+ // backend, the only difference is that they are not used to actaully
+ // access memory by the instruction.
+ enum class ConstraintCode : uint32_t {
+ Unknown = 0,
+ es,
+ i,
+ k,
+ m,
+ o,
+ v,
+ A,
+ Q,
+ R,
+ S,
+ T,
+ Um,
+ Un,
+ Uq,
+ Us,
+ Ut,
+ Uv,
+ Uy,
+ X,
+ Z,
+ ZB,
+ ZC,
+ Zy,
+
+ // Address constraints
+ p,
+ ZQ,
+ ZR,
+ ZS,
+ ZT,
+
+ Max = ZT,
+ };
+
// These are helper methods for dealing with flags in the INLINEASM SDNode
// in the backend.
//
@@ -375,11 +373,14 @@ class InlineAsm final : public Value {
return true;
}
- // TODO: convert to enum?
- unsigned getMemoryConstraintID() const {
+ ConstraintCode getMemoryConstraintID() const {
assert((isMemKind() || isFuncKind()) &&
"Not expected mem or function flag!");
- return getData();
+ uint32_t D = getData();
+ assert(D < static_cast<uint32_t>(ConstraintCode::Max) &&
+ D >= static_cast<uint32_t>(ConstraintCode::Unknown) &&
+ "unexpected value for memory constraint");
+ return static_cast<ConstraintCode>(D);
}
/// setMatchingOp - Augment an existing flag with information indicating
@@ -403,12 +404,11 @@ class InlineAsm final : public Value {
/// setMemConstraint - Augment an existing flag with the constraint code for
/// a memory constraint.
- void setMemConstraint(unsigned Constraint) {
+ void setMemConstraint(ConstraintCode C) {
assert((isMemKind() || isFuncKind()) &&
"Flag is not a memory or function constraint!");
- assert(Constraint <= Constraints_Max && "Unknown constraint ID");
assert(getData() == 0 && "Mem constraint already set");
- setData(Constraint);
+ setData(static_cast<uint32_t>(C));
}
/// clearMemConstraint - Similar to setMemConstraint(0), but without the
/// assertion checking that the constraint has not been set previously.
@@ -443,61 +443,61 @@ class InlineAsm final : public Value {
return Result;
}
- static StringRef getMemConstraintName(unsigned Constraint) {
- switch (Constraint) {
- case InlineAsm::Constraint_es:
+ static StringRef getMemConstraintName(const ConstraintCode C) {
+ switch (C) {
+ case ConstraintCode::es:
return "es";
- case InlineAsm::Constraint_i:
+ case ConstraintCode::i:
return "i";
- case InlineAsm::Constraint_k:
+ case ConstraintCode::k:
return "k";
- case InlineAsm::Constraint_m:
+ case ConstraintCode::m:
return "m";
- case InlineAsm::Constraint_o:
+ case ConstraintCode::o:
return "o";
- case InlineAsm::Constraint_v:
+ case ConstraintCode::v:
return "v";
- case InlineAsm::Constraint_Q:
+ case ConstraintCode::Q:
return "Q";
- case InlineAsm::Constraint_R:
+ case ConstraintCode::R:
return "R";
- case InlineAsm::Constraint_S:
+ case ConstraintCode::S:
return "S";
- case InlineAsm::Constraint_T:
+ case ConstraintCode::T:
return "T";
- case InlineAsm::Constraint_Um:
+ case ConstraintCode::Um:
return "Um";
- case InlineAsm::Constraint_Un:
+ case ConstraintCode::Un:
return "Un";
- case InlineAsm::Constraint_Uq:
+ case ConstraintCode::Uq:
return "Uq";
- case InlineAsm::Constraint_Us:
+ case ConstraintCode::Us:
return "Us";
- case InlineAsm::Constraint_Ut:
+ case ConstraintCode::Ut:
return "Ut";
- case InlineAsm::Constraint_Uv:
+ case ConstraintCode::Uv:
return "Uv";
- case InlineAsm::Constraint_Uy:
+ case ConstraintCode::Uy:
return "Uy";
- case InlineAsm::Constraint_X:
+ case ConstraintCode::X:
return "X";
- case InlineAsm::Constraint_Z:
+ case ConstraintCode::Z:
return "Z";
- case InlineAsm::Constraint_ZB:
+ case ConstraintCode::ZB:
return "ZB";
- case InlineAsm::Constraint_ZC:
+ case ConstraintCode::ZC:
return "ZC";
- case InlineAsm::Constraint_Zy:
+ case ConstraintCode::Zy:
return "Zy";
- case InlineAsm::Constraint_p:
+ case ConstraintCode::p:
return "p";
- case InlineAsm::Constraint_ZQ:
+ case ConstraintCode::ZQ:
return "ZQ";
- case InlineAsm::Constraint_ZR:
+ case ConstraintCode::ZR:
return "ZR";
- case InlineAsm::Constraint_ZS:
+ case ConstraintCode::ZS:
return "ZS";
- case InlineAsm::Constraint_ZT:
+ case ConstraintCode::ZT:
return "ZT";
default:
llvm_unreachable("Unknown memory constraint");
diff --git a/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp b/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
index 9944ba15997687a..00dba57fcb80227 100644
--- a/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
@@ -373,9 +373,9 @@ bool InlineAsmLowering::lowerInlineAsm(
switch (OpInfo.Type) {
case InlineAsm::isOutput:
if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
- unsigned ConstraintID =
+ const InlineAsm::ConstraintCode ConstraintID =
TLI->getInlineAsmMemConstraint(OpInfo.ConstraintCode);
- assert(ConstraintID != InlineAsm::Constraint_Unknown &&
+ assert(ConstraintID != InlineAsm::ConstraintCode::Unknown &&
"Failed to convert memory constraint code to constraint id.");
// Add information to the INLINEASM instruction to know about this
@@ -517,7 +517,7 @@ bool InlineAsmLowering::lowerInlineAsm(
assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
- unsigned ConstraintID =
+ const InlineAsm::ConstraintCode ConstraintID =
TLI->getInlineAsmMemConstraint(OpInfo.ConstraintCode);
InlineAsm::Flag OpFlags(InlineAsm::Kind::Mem, 1);
OpFlags.setMemConstraint(ConstraintID);
diff --git a/llvm/lib/CodeGen/MachineInstr.cpp b/llvm/lib/CodeGen/MachineInstr.cpp
index 8cc3391e0d96a3d..d8467e2af8786ec 100644
--- a/llvm/lib/CodeGen/MachineInstr.cpp
+++ b/llvm/lib/CodeGen/MachineInstr.cpp
@@ -1778,7 +1778,7 @@ void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST,
}
if (F.isMemKind()) {
- const unsigned MCID = F.getMemoryConstraintID();
+ const InlineAsm::ConstraintCode MCID = F.getMemoryConstraintID();
OS << ":" << InlineAsm::getMemConstraintName(MCID);
}
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 738dd10633db6a5..720fc4944161225 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -9281,9 +9281,9 @@ void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call,
switch (OpInfo.Type) {
case InlineAsm::isOutput:
if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
- unsigned ConstraintID =
+ const InlineAsm::ConstraintCode ConstraintID =
TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
- assert(ConstraintID != InlineAsm::Constraint_Unknown &&
+ assert(ConstraintID != InlineAsm::ConstraintCode::Unknown &&
"Failed to convert memory constraint code to constraint id.");
// Add information to the INLINEASM node to know about this output.
@@ -9413,9 +9413,9 @@ void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call,
TLI.getPointerTy(DAG.getDataLayout()) &&
"Memory operands expect pointer values");
- unsigned ConstraintID =
+ const InlineAsm::ConstraintCode ConstraintID =
TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
- assert(ConstraintID != InlineAsm::Constraint_Unknown &&
+ assert(ConstraintID != InlineAsm::ConstraintCode::Unknown &&
"Failed to convert memory constraint code to constraint id.");
// Add information to the INLINEASM node to know about this input.
@@ -9429,9 +9429,9 @@ void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call,
}
if (OpInfo.ConstraintType == TargetLowering::C_Address) {
- unsigned ConstraintID =
+ const InlineAsm::ConstraintCode ConstraintID =
TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
- assert(ConstraintID != InlineAsm::Constraint_Unknown &&
+ assert(ConstraintID != InlineAsm::ConstraintCode::Unknown &&
"Failed to convert memory constraint code to constraint id.");
InlineAsm::Flag ResOpType(InlineAsm::Kind::Mem, 1);
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index a7873241df62e52..91b9d77eed70596 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -2101,7 +2101,8 @@ void SelectionDAGISel::SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops,
// Otherwise, this is a memory operand. Ask the target to select it.
std::vector<SDValue> SelOps;
- unsigned ConstraintID = Flags.getMemoryConstraintID();
+ const InlineAsm::ConstraintCode ConstraintID =
+ Flags.getMemoryConstraintID();
if (SelectInlineAsmMemoryOperand(InOps[i+1], ConstraintID, SelOps))
report_fatal_error("Could not match memory address. Inline asm"
" failure!");
diff --git a/llvm/lib/CodeGen/TargetInstrInfo.cpp b/llvm/lib/CodeGen/TargetInstrInfo.cpp
index 686044ea572ac0d..bf1605f06bd88d6 100644
--- a/llvm/lib/CodeGen/TargetInstrInfo.cpp
+++ b/llvm/lib/CodeGen/TargetInstrInfo.cpp
@@ -1622,7 +1622,7 @@ std::string TargetInstrInfo::createMIROperandComment(
}
if (F.isMemKind()) {
- const unsigned MCID = F.getMemoryConstraintID();
+ InlineAsm::ConstraintCode MCID = F.getMemoryConstraintID();
OS << ":" << InlineAsm::getMemConstraintName(MCID);
}
diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
index 60a155a86667e89..740995849740fef 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -61,9 +61,10 @@ class AArch64DAGToDAGISel : public SelectionDAGISel {
/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
/// inline asm expressions.
- bool SelectInlineAsmMemoryOperand(const SDValue &Op,
- unsigned ConstraintID,
- std::vector<SDValue> &OutOps) override;
+ bool
+ SelectInlineAsmMemoryOperand(const SDValue &Op,
+ const InlineAsm::ConstraintCode ConstraintID,
+ std::vector<SDValue> &OutOps) override;
template <signed Low, signed High, signed Scale>
bool SelectRDVLImm(SDValue N, SDValue &Imm);
@@ -533,13 +534,14 @@ static bool isIntImmediateEq(SDValue N, const uint64_t ImmExpected) {
#endif
bool AArch64DAGToDAGISel::SelectInlineAsmMemoryOperand(
- const SDValue &Op, unsigned ConstraintID, std::vector<SDValue> &OutOps) {
+ const SDValue &Op, const InlineAsm::ConstraintCode ConstraintID,
+ std::vector<SDValue> &OutOps) {
switch(ConstraintID) {
default:
llvm_unreachable("Unexpected asm memory constraint");
- case InlineAsm::Constraint_m:
- case InlineAsm::Constraint_o:
- case InlineAsm::Constraint_Q:
+ case InlineAsm::ConstraintCode::m:
+ case InlineAsm::ConstraintCode::o:
+ case InlineAsm::ConstraintCode::Q:
// We need to make sure that this one operand does not end up in XZR, thus
// require the address to be in a PointerRegClass register.
const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
index 67c344318e0d3ec..f2696b6b97593a1 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
@@ -1169,9 +1169,10 @@ class AArch64TargetLowering : public TargetLowering {
std::vector<SDValue> &Ops,
SelectionDAG &DAG) const override;
- unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
+ InlineAsm::ConstraintCode
+ getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
if (ConstraintCode == "Q")
- return InlineAsm::Constraint_Q;
+ return InlineAsm::ConstraintCode::Q;
// FIXME: clang has code for 'Ump', 'Utf', 'Usa', and 'Ush' but these are
// followed by llvm_unreachable so we'll leave them unimplemented in
// the backend for now.
diff --git a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
index 5f4fab0675824fd..9956b1b040b329d 100644
--- a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -331,8 +331,10 @@ class ARMDAGToDAGISel : public SelectionDAGISel {
/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
/// inline asm expressions.
- bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
- std::vector<SDValue> &OutOps) override;
+ bool
+ SelectInlineAsmMemoryOperand(const SDValue &Op,
+ const InlineAsm::ConstraintCode ConstraintID,
+ std::vector<SDValue> &OutOps) override;
// Form pairs of consecutive R, S, D, or Q registers.
SDNode *createGPRPairNode(EVT VT, SDValue V0, SDValue V1);
@@ -5864,23 +5866,22 @@ bool ARMDAGToDAGISel::tryInlineAsm(SDNode *N){
return true;
}
-
-bool ARMDAGToDAGISel::
-SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
- std::vector<SDValue> &OutOps) {
+bool ARMDAGToDAGISel::SelectInlineAsmMemoryOperand(
+ const SDValue &Op, const InlineAsm::ConstraintCode ConstraintID,
+ std::vector<SDValue> &OutOps) {
switch(ConstraintID) {
default:
llvm_unreachable("Unexpected asm memory constraint");
- case InlineAsm::Constraint_m:
- case InlineAsm::Constraint_o:
- case InlineAsm::Constraint_Q:
- case InlineAsm::Constraint_Um:
- case InlineAsm::Constraint_Un:
- case InlineAsm::Constraint_Uq:
- case InlineAsm::Constraint_Us:
- case InlineAsm::Constraint_Ut:
- case InlineAsm::Constraint_Uv:
- case InlineAsm::Constraint_Uy:
+ case InlineAsm::ConstraintCode::m:
+ case InlineAsm::ConstraintCode::o:
+ case InlineAsm::ConstraintCode::Q:
+ case InlineAsm::ConstraintCode::Um:
+ case InlineAsm::ConstraintCode::Un:
+ case InlineAsm::ConstraintCode::Uq:
+ case InlineAsm::ConstraintCode::Us:
+ case InlineAsm::ConstraintCode::Ut:
+ case InlineAsm::ConstraintCode::Uv:
+ case InlineAsm::ConstraintCode::Uy:
// Require the address to be in a register. That is safe for all ARM
// variants and it is hard to do anything much smarter without knowing
// how the operand is used.
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.h b/llvm/lib/Target/ARM/ARMISelLowering.h
index 2dd54602ef61b9c..efa82386768605d 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.h
+++ b/llvm/lib/Target/ARM/ARMISelLowering.h
@@ -534,29 +534,29 @@ class VectorType;
std::vector<SDValue> &Ops,
SelectionDAG &DAG) const override;
- unsigned
+ InlineAsm::ConstraintCode
getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
if (ConstraintCode == "Q")
- return InlineAsm::Constraint_Q;
- else if (ConstraintCode.size() == 2) {
+ return InlineAsm::ConstraintCode::Q;
+ if (ConstraintCode.size() == 2) {
if (ConstraintCode[0] == 'U') {
switch(ConstraintCode[1]) {
default:
break;
case 'm':
- return InlineAsm::Constraint_Um;
+ return InlineAsm::ConstraintCode::Um;
case 'n':
- return InlineAsm::Constraint_Un;
+ return InlineAsm::ConstraintCode::Un;
case 'q':
- return InlineAsm::Constraint_Uq;
+ return InlineAsm::ConstraintCode::Uq;
case 's':
- return InlineAsm::Constraint_Us;
+ return InlineAsm::ConstraintCode::Us;
case 't':
- return InlineAsm::Constraint_Ut;
+ return InlineAsm::ConstraintCode::Ut;
case 'v':
- return InlineAsm::Constraint_Uv;
+ return InlineAsm::ConstraintCode::Uv;
case 'y':
- return InlineAsm::Constraint_Uy;
+ return InlineAsm::ConstraintCode::Uy;
}
}
}
diff --git a/llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp b/llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp
index bbb1de40be63409..7b0b050e9a051c9 100644
--- a/llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp
@@ -43,7 +43,8 @@ class AVRDAGToDAGISel : public SelectionDAGISel {
bool selectIndexedLoad(SDNode *N);
unsigned selectIndexedProgMemLoad(const LoadSDNode *LD, MVT VT, int Bank);
- bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintCode,
+ bool SelectInlineAsmMemoryOperand(const SDValue &Op,
+ InlineAsm::ConstraintCode ConstraintCode,
std::vector<SDValue> &OutOps) override;
// Include the pieces autogenerated from the target description.
@@ -200,9 +201,10 @@ unsigned AVRDAGToDAGISel::selectIndexedProgMemLoad(const LoadSDNode *LD, MVT VT,
}
bool AVRDAGToDAGISel::SelectInlineAsmMemoryOperand(
- const SDValue &Op, unsigned ConstraintCode, std::vector<SDValue> &OutOps) {
- assert((ConstraintCode == InlineAsm::Constraint_m ||
- ConstraintCode == InlineAsm::Constraint_Q) &&
+ const SDValue &Op, const InlineAsm::ConstraintCode ConstraintCode,
+ std::vector<SDValue> &OutOps) {
+ assert((ConstraintCode == InlineAsm::ConstraintCode::m ||
+ ConstraintCode == InlineAsm::ConstraintCode::Q) &&
"Unexpected asm memory constraint");
MachineRegisterInfo &RI = MF->getRegInfo();
diff --git a/llvm/lib/Target/AVR/AVRISelLowering.cpp b/llvm/lib/Target/AVR/AVRISelLowering.cpp
index 2b7370409085165..4f5a48bd05a4e86 100644
--- a/llvm/lib/Target/AVR/AVRISelLowering.cpp
+++ b/llvm/lib/Target/AVR/AVRISelLowering.cpp
@@ -2521,13 +2521,13 @@ AVRTargetLowering::getConstraintType(StringRef Constraint) const {
return TargetLowering::getConstraintType(Constraint);
}
-unsigned
+InlineAsm::ConstraintCode
AVRTargetLowering::getInlineAsmMemConstraint(StringRef ConstraintCode) const {
// Not sure if this is actually the right thing to do, but we got to do
// *something* [agnat]
switch (ConstraintCode[0]) {
case 'Q':
- return InlineAsm::Constraint_Q;
+ return InlineAsm::ConstraintCode::Q;
}
return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
}
diff --git a/llvm/lib/Target/AVR/AVRISelLowering.h b/llvm/lib/Target/AVR/AVRISelLowering.h
index b696bebe7136f42..6815b519bebf74d 100644
--- a/llvm/lib/Target/AVR/AVRISelLowering.h
+++ b/llvm/lib/Target/AVR/AVRISelLowering.h
@@ -133,7 +133,8 @@ class AVRTargetLowering : public TargetLowering {
getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
StringRef Constraint, MVT VT) const override;
- unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override;
+ InlineAsm::ConstraintCode
+ getInlineAsmMemConstraint(StringRef ConstraintCode) const override;
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
std::vector<SDValue> &Ops,
diff --git a/llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp b/llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp
index 32fa4ea1e302b68..b53ae6b6f4ca0ed 100644
--- a/llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp
+++ b/llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp
@@ -48,8 +48,10 @@ class CSKYDAGToDAGISel : public SelectionDAGISel {
SDNode *createGPRPairNode(EVT VT, SDValue V0, SDValue V1);
- bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
- std::vector<SDValue> &OutOps) override;
+ bool
+ SelectInlineAsmMemoryOperand(const SDValue &Op,
+ const InlineAsm::ConstraintCode ConstraintID,
+ std::vector<SDValue> &OutOps) override;
#include "CSKYGenDAGISel.inc"
};
@@ -383,9 +385,10 @@ SDNode *CSKYDAGToDAGISel::createGPRPairNode(EVT VT, SDValue V0, SDValue V1) {
}
bool CSKYDAGToDAGISel::SelectInlineAsmMemoryOperand(
- const SDValue &Op, unsigned ConstraintID, std::vector<SDValue> &OutOps) {
+ const SDValue &Op, const InlineAsm::ConstraintCode ConstraintID,
+ std::vector<SDValue> &OutOps) {
switch (ConstraintID) {
- case InlineAsm::Constraint_m:
+ case InlineAsm::ConstraintCode::m:
// We just support simple memory operands that have a single address
// operand and need no special handling.
OutOps.push_back(Op);
diff --git a/llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp b/llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp
index e33654ea3f18665..8bf317b320f52c8 100644
--- a/llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp
+++ b/llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp
@@ -227,8 +227,10 @@ class M68kDAGToDAGISel : public SelectionDAGISel {
bool SelectPCD(SDNode *Parent, SDValue N, SDValue &Imm);
bool SelectPCI(SDNode *Parent, SDValue N, SDValue &Imm, SDValue &Index);
- bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
- std::vector<SDValue> &OutOps) override;
+ bool
+ SelectInlineAsmMemoryOperand(const SDValue &Op,
+ const InlineAsm::ConstraintCode ConstraintID,
+ std::vector<SDValue> &OutOps) override;
// If Address Mode represents Frame Index store FI in Disp and
// Displacement bit size in Base. These values are read symmetrically by
@@ -953,7 +955,8 @@ bool M68kDAGToDAGISel::SelectARI(SDNode *Parent, SDValue N, SDValue &Base) {
}
bool M68kDAGToDAGISel::SelectInlineAsmMemoryOperand(
- const SDValue &Op, unsigned ConstraintID, std::vector<SDValue> &OutOps) {
+ const SDValue &Op, const InlineAsm::ConstraintCode ConstraintID,
+ std::vector<SDValue> &OutOps) {
// In order to tell AsmPrinter the exact addressing mode we select here, which
// might comprise of multiple SDValues (hence MachineOperands), a 32-bit
// immediate value is prepended to the list of selected SDValues to indicate
@@ -966,7 +969,7 @@ bool M68kDAGToDAGISel::SelectInlineAsmMemoryOperand(
switch (ConstraintID) {
// Generic memory operand.
- case InlineAsm::Constraint_m: {
+ case InlineAsm::ConstraintCode::m: {
// Try every supported (memory) addressing modes.
SDValue Operands[4];
@@ -997,7 +1000,7 @@ bool M68kDAGToDAGISel::SelectInlineAsmMemoryOperand(
return true;
}
// 'Q': Address register indirect addressing.
- case InlineAsm::Constraint_Q: {
+ case InlineAsm::ConstraintCode::Q: {
SDValue AMKind, Base;
// 'j' addressing mode.
// TODO: Add support for 'o' and 'e' after their
@@ -1009,7 +1012,7 @@ bool M68kDAGToDAGISel::SelectInlineAsmMemoryOperand(
return true;
}
// 'U': Address register indirect w/ constant offset addressing.
- case InlineAsm::Constraint_Um: {
+ case InlineAsm::ConstraintCode::Um: {
SDValue AMKind, Base, Offset;
// 'p' addressing mode.
if (SelectARID(nullptr, Op, Offset, Base) && addKind(AMKind, AMK::p)) {
diff --git a/llvm/lib/Target/M68k/M68kISelLowering.cpp b/llvm/lib/Target/M68k/M68kISelLowering.cpp
index ae3c348a59999e1..82eb1edafc1b211 100644
--- a/llvm/lib/Target/M68k/M68kISelLowering.cpp
+++ b/llvm/lib/Target/M68k/M68kISelLowering.cpp
@@ -204,11 +204,12 @@ M68kTargetLowering::getExceptionSelectorRegister(const Constant *) const {
return M68k::D1;
}
-unsigned
+InlineAsm::ConstraintCode
M68kTargetLowering::getInlineAsmMemConstraint(StringRef ConstraintCode) const {
- return StringSwitch<unsigned>(ConstraintCode)
- .Case("Q", InlineAsm::Constraint_Q)
- .Case("U", InlineAsm::Constraint_Um) // We borrow Constraint_Um for 'U'.
+ return StringSwitch<InlineAsm::ConstraintCode>(ConstraintCode)
+ .Case("Q", InlineAsm::ConstraintCode::Q)
+ .Case("U",
+ InlineAsm::ConstraintCode::Um) // We borrow Constraint_Um for 'U'.
.Default(TargetLowering::getInlineAsmMemConstraint(ConstraintCode));
}
diff --git a/llvm/lib/Target/M68k/M68kISelLowering.h b/llvm/lib/Target/M68k/M68kISelLowering.h
index 5f279b3dcbd3ee4..37e66695fde9036 100644
--- a/llvm/lib/Target/M68k/M68kISelLowering.h
+++ b/llvm/lib/Target/M68k/M68kISelLowering.h
@@ -187,7 +187,8 @@ class M68kTargetLowering : public TargetLowering {
Register
getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
- unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override;
+ InlineAsm::ConstraintCode
+ getInlineAsmMemConstraint(StringRef ConstraintCode) const override;
private:
unsigned GetAlignedArgumentStackSize(unsigned StackSize,
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index c6cefc000b3f746..78251f2c5107722 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -2163,12 +2163,13 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
}
bool RISCVDAGToDAGISel::SelectInlineAsmMemoryOperand(
- const SDValue &Op, unsigned ConstraintID, std::vector<SDValue> &OutOps) {
+ const SDValue &Op, const InlineAsm::ConstraintCode ConstraintID,
+ std::vector<SDValue> &OutOps) {
// Always produce a register and immediate operand, as expected by
// RISCVAsmPrinter::PrintAsmMemoryOperand.
switch (ConstraintID) {
- case InlineAsm::Constraint_o:
- case InlineAsm::Constraint_m: {
+ case InlineAsm::ConstraintCode::o:
+ case InlineAsm::ConstraintCode::m: {
SDValue Op0, Op1;
bool Found = SelectAddrRegImm(Op, Op0, Op1);
assert(Found && "SelectAddrRegImm should always succeed");
@@ -2177,7 +2178,7 @@ bool RISCVDAGToDAGISel::SelectInlineAsmMemoryOperand(
OutOps.push_back(Op1);
return false;
}
- case InlineAsm::Constraint_A:
+ case InlineAsm::ConstraintCode::A:
OutOps.push_back(Op);
OutOps.push_back(
CurDAG->getTargetConstant(0, SDLoc(Op), Subtarget->getXLenVT()));
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
index fbc1520a54ba071..4248a5e45115390 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
@@ -43,8 +43,10 @@ class RISCVDAGToDAGISel : public SelectionDAGISel {
void Select(SDNode *Node) override;
- bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
- std::vector<SDValue> &OutOps) override;
+ bool
+ SelectInlineAsmMemoryOperand(const SDValue &Op,
+ const InlineAsm::ConstraintCode ConstraintID,
+ std::vector<SDValue> &OutOps) override;
bool SelectAddrFrameIndex(SDValue Addr, SDValue &Base, SDValue &Offset);
bool SelectFrameAddrRegImm(SDValue Addr, SDValue &Base, SDValue &Offset);
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 4ff264635cda248..1e446b5d579b8d8 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -17395,13 +17395,13 @@ RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
return Res;
}
-unsigned
+InlineAsm::ConstraintCode
RISCVTargetLowering::getInlineAsmMemConstraint(StringRef ConstraintCode) const {
// Currently only support length 1 constraints.
if (ConstraintCode.size() == 1) {
switch (ConstraintCode[0]) {
case 'A':
- return InlineAsm::Constraint_A;
+ return InlineAsm::ConstraintCode::A;
default:
break;
}
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h
index 44d421c9cae73b0..271391826e35f9e 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -566,7 +566,8 @@ class RISCVTargetLowering : public TargetLowering {
ConstraintType getConstraintType(StringRef Constraint) const override;
- unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override;
+ InlineAsm::ConstraintCode
+ getInlineAsmMemConstraint(StringRef ConstraintCode) const override;
std::pair<unsigned, const TargetRegisterClass *>
getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
index 5ebb0a8239aa38b..909a5f2e84799f3 100644
--- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -258,9 +258,10 @@ namespace {
bool isProfitableToFormMaskedOp(SDNode *N) const;
/// Implement addressing mode selection for inline asm expressions.
- bool SelectInlineAsmMemoryOperand(const SDValue &Op,
- unsigned ConstraintID,
- std::vector<SDValue> &OutOps) override;
+ bool
+ SelectInlineAsmMemoryOperand(const SDValue &Op,
+ const InlineAsm::ConstraintCode ConstraintID,
+ std::vector<SDValue> &OutOps) override;
void emitSpecialCodeForMain();
@@ -6323,18 +6324,18 @@ void X86DAGToDAGISel::Select(SDNode *Node) {
SelectCode(Node);
}
-bool X86DAGToDAGISel::
-SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
- std::vector<SDValue> &OutOps) {
+bool X86DAGToDAGISel::SelectInlineAsmMemoryOperand(
+ const SDValue &Op, const InlineAsm::ConstraintCode ConstraintID,
+ std::vector<SDValue> &OutOps) {
SDValue Op0, Op1, Op2, Op3, Op4;
switch (ConstraintID) {
default:
llvm_unreachable("Unexpected asm memory constraint");
- case InlineAsm::Constraint_o: // offsetable ??
- case InlineAsm::Constraint_v: // not offsetable ??
- case InlineAsm::Constraint_m: // memory
- case InlineAsm::Constraint_X:
- case InlineAsm::Constraint_p: // address
+ case InlineAsm::ConstraintCode::o: // offsetable ??
+ case InlineAsm::ConstraintCode::v: // not offsetable ??
+ case InlineAsm::ConstraintCode::m: // memory
+ case InlineAsm::ConstraintCode::X:
+ case InlineAsm::ConstraintCode::p: // address
if (!selectAddr(nullptr, Op, Op0, Op1, Op2, Op3, Op4))
return true;
break;
diff --git a/llvm/lib/Target/X86/X86ISelLowering.h b/llvm/lib/Target/X86/X86ISelLowering.h
index 5689543fcd1fa2c..4d45a0a58442105 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.h
+++ b/llvm/lib/Target/X86/X86ISelLowering.h
@@ -1279,10 +1279,10 @@ namespace llvm {
std::vector<SDValue> &Ops,
SelectionDAG &DAG) const override;
- unsigned
+ InlineAsm::ConstraintCode
getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
if (ConstraintCode == "v")
- return InlineAsm::Constraint_v;
+ return InlineAsm::ConstraintCode::v;
return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
}
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