[llvm] [InstCombine][RISCV] Convert VPIntrinsics with splat operands to splats (PR #65706)

[Luke Lau via llvm-commits]

================
@@ -729,6 +730,172 @@ bool VectorCombine::foldBitcastShuf(Instruction &I) {
   return true;
 }
 
+/// VP Intrinsics whose vector operands are both splat values may be simplified
+/// into the scalar version of the operation and the result is splatted. This
+/// can lead to scalarization down the line.
+bool VectorCombine::scalarizeVPIntrinsic(VPIntrinsic &VPI) {
+  Value *Op0 = VPI.getArgOperand(0);
+  Value *Op1 = VPI.getArgOperand(1);
+
+  if (!isSplatValue(Op0) || !isSplatValue(Op1))
+    return false;
+
+  // For the binary VP intrinsics supported here, the result on disabled lanes
+  // is a poison value. For now, only do this simplification if all lanes
+  // are active.
+  // TODO: Relax the condition that all lanes are active by using insertelement
+  // on inactive lanes.
+  auto IsAllTrueMask = [](Value *MaskVal) {
+    if (Value *SplattedVal = getSplatValue(MaskVal))
+      if (auto *ConstValue = dyn_cast<Constant>(SplattedVal))
+        return ConstValue->isAllOnesValue();
+    return false;
+  };
+  if (!IsAllTrueMask(VPI.getArgOperand(2)))
+    return false;
+
+  DenseMap<Intrinsic::ID, unsigned> VPIntrinsicToScalar(
+      {{Intrinsic::vp_add, Instruction::Add},
+       {Intrinsic::vp_sub, Instruction::Sub},
+       {Intrinsic::vp_mul, Instruction::Mul},
+       {Intrinsic::vp_ashr, Instruction::AShr},
+       {Intrinsic::vp_lshr, Instruction::LShr},
+       {Intrinsic::vp_shl, Instruction::Shl},
+       {Intrinsic::vp_or, Instruction::Or},
+       {Intrinsic::vp_and, Instruction::And},
+       {Intrinsic::vp_xor, Instruction::Xor},
+       {Intrinsic::vp_fadd, Instruction::FAdd},
+       {Intrinsic::vp_fsub, Instruction::FSub},
+       {Intrinsic::vp_fmul, Instruction::FMul},
+       {Intrinsic::vp_sdiv, Instruction::SDiv},
+       {Intrinsic::vp_udiv, Instruction::UDiv},
+       {Intrinsic::vp_srem, Instruction::SRem},
+       {Intrinsic::vp_urem, Instruction::URem}});
----------------
lukel97 wrote:

There's an existing mapping from vp intrinsic->regular opcode defined in `include/llvm/IR/VPIntrinsics.def`, can we reuse it and replace this with `VPIntrinsic::getFunctionalOpcodeForVP`? 

https://github.com/llvm/llvm-project/pull/65706