[llvm] [AArch64] Separate PNR into its own Register Class (PR #65306)

[via llvm-commits]

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@@ -1348,9 +1348,14 @@ void AArch64InstPrinter::printPredicateAsCounter(const MCInst *MI,
                                                  const MCSubtargetInfo &STI,
                                                  raw_ostream &O) {
   unsigned Reg = MI->getOperand(OpNum).getReg();
+  O << "pn";
+  if (Reg >= AArch64::P0 && Reg <= AArch64::P15)
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sdesmalen-arm wrote:

Is this change needed? I would expect a predicate-as-counter to be printed as a predicate-as-mask, but not the other way around.

https://github.com/llvm/llvm-project/pull/65306