[llvm] [RISCV] Add tests where bin ops of splats could be scalarized. NFC (PR #65747)

[Luke Lau via llvm-commits]

lukel97 wrote:

> Will you try and scalarize instructions like div and rem which are more expensive and may need cost modeling? Will you scalarize f16 vectors in the case that there is no f16 scalar, which requires extra instructions to convert to f32 first?
> 
> If so, it could be nice to have tests for these instructions/types.

The combine already exists in DAGCombiner, but at the SelectionDAG level it's pretty simple and doesn't do any cost modelling. From a quick scan it does look like it tries to scalarize UDIV/SDIV. It also looks like it doesn't try to scalarize it if there isn't a matching legal scalar operation for the type, e.g. here's the "cost model":

```c++
  bool IsBothSplatVector = N0.getOpcode() == ISD::SPLAT_VECTOR &&
                           N1.getOpcode() == ISD::SPLAT_VECTOR;
  if (!Src0 || !Src1 || Index0 != Index1 ||
      Src0.getValueType().getVectorElementType() != EltVT ||
      Src1.getValueType().getVectorElementType() != EltVT ||
      !(IsBothSplatVector || TLI.isExtractVecEltCheap(VT, Index0)) ||
      !TLI.isOperationLegalOrCustom(Opcode, EltVT))
    return SDValue();
```

I agree though, will add those tests to confirm that it doesn't attempt to scalarize them.

https://github.com/llvm/llvm-project/pull/65747