[llvm] [JumpThreading] Invalidate LVI after `combineMetadataForCSE`. (PR #65219)
via llvm-commits
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Sat Sep 2 23:26:52 PDT 2023
https://github.com/DianQK created https://github.com/llvm/llvm-project/pull/65219:
Fixes #65195.
LVI information may be out of date after `combineMetadataForCSE`.
>From 543fd1854da4ee918c50e9ac87e49cf4df4534a9 Mon Sep 17 00:00:00 2001
From: DianQK <dianqk at dianqk.net>
Date: Sun, 3 Sep 2023 12:18:57 +0800
Subject: [PATCH 1/2] [JumpThreading][NFC] Pre-commit for invalid LVI.
---
.../JumpThreading/invalidate-lvi.ll | 53 +++++++++++++++++++
1 file changed, 53 insertions(+)
create mode 100644 llvm/test/Transforms/JumpThreading/invalidate-lvi.ll
diff --git a/llvm/test/Transforms/JumpThreading/invalidate-lvi.ll b/llvm/test/Transforms/JumpThreading/invalidate-lvi.ll
new file mode 100644
index 000000000000000..9c5cbfac62d9fb5
--- /dev/null
+++ b/llvm/test/Transforms/JumpThreading/invalidate-lvi.ll
@@ -0,0 +1,53 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3
+; RUN: opt -S -passes=jump-threading < %s | FileCheck %s
+
+declare void @set_value(ptr)
+
+declare void @bar()
+
+define void @foo(i1 %0) {
+; CHECK-LABEL: define void @foo(
+; CHECK-SAME: i1 [[TMP0:%.*]]) {
+; CHECK-NEXT: start:
+; CHECK-NEXT: [[V:%.*]] = alloca i64, align 8
+; CHECK-NEXT: call void @set_value(ptr [[V]])
+; CHECK-NEXT: [[L1:%.*]] = load i64, ptr [[V]], align 8
+; CHECK-NEXT: br i1 [[TMP0]], label [[BB0:%.*]], label [[BB4:%.*]]
+; CHECK: bb0:
+; CHECK-NEXT: [[C1:%.*]] = icmp eq i64 [[L1]], 0
+; CHECK-NEXT: br i1 [[C1]], label [[BB1:%.*]], label [[BB4]]
+; CHECK: bb1:
+; CHECK-NEXT: store i64 0, ptr [[V]], align 8
+; CHECK-NEXT: br label [[BB4]]
+; CHECK: bb4:
+; CHECK-NEXT: [[L2:%.*]] = phi i64 [ 0, [[BB1]] ], [ [[L1]], [[BB0]] ], [ [[L1]], [[START:%.*]] ]
+; CHECK-NEXT: ret void
+;
+start:
+ %v = alloca i64, align 8
+ call void @set_value(ptr %v)
+ %l1 = load i64, ptr %v, align 8, !range !0
+ br i1 %0, label %bb0, label %bb2
+
+bb0: ; preds = %start
+ %c1 = icmp eq i64 %l1, 0
+ br i1 %c1, label %bb1, label %bb2
+
+bb1: ; preds = %bb0
+ store i64 0, ptr %v, align 8
+ br label %bb2
+
+bb2: ; preds = %bb1, %bb0, %start
+ %l2 = load i64, ptr %v, align 8
+ %1 = icmp eq i64 %l2, 2
+ br i1 %1, label %bb3, label %bb4
+
+bb3: ; preds = %bb2
+ call void @bar()
+ ret void
+
+bb4: ; preds = %bb2
+ ret void
+}
+
+!0 = !{i64 0, i64 2}
>From 1eca78a450850aeea9f858296b3e90ca5325b982 Mon Sep 17 00:00:00 2001
From: DianQK <dianqk at dianqk.net>
Date: Sun, 3 Sep 2023 12:23:33 +0800
Subject: [PATCH 2/2] [JumpThreading] Invalidate LVI after
`combineMetadataForCSE`.
---
llvm/lib/Transforms/Scalar/JumpThreading.cpp | 2 ++
.../Transforms/JumpThreading/invalidate-lvi.ll | 16 +++++++++++-----
2 files changed, 13 insertions(+), 5 deletions(-)
diff --git a/llvm/lib/Transforms/Scalar/JumpThreading.cpp b/llvm/lib/Transforms/Scalar/JumpThreading.cpp
index 180e6b4c8238809..3e0049c66c1503c 100644
--- a/llvm/lib/Transforms/Scalar/JumpThreading.cpp
+++ b/llvm/lib/Transforms/Scalar/JumpThreading.cpp
@@ -1269,6 +1269,7 @@ bool JumpThreadingPass::simplifyPartiallyRedundantLoad(LoadInst *LoadI) {
if (IsLoadCSE) {
LoadInst *NLoadI = cast<LoadInst>(AvailableVal);
combineMetadataForCSE(NLoadI, LoadI, false);
+ LVI->eraseBlock(NLoadI->getParent());
};
// If the returned value is the load itself, replace with poison. This can
@@ -1461,6 +1462,7 @@ bool JumpThreadingPass::simplifyPartiallyRedundantLoad(LoadInst *LoadI) {
for (LoadInst *PredLoadI : CSELoads) {
combineMetadataForCSE(PredLoadI, LoadI, true);
+ LVI->eraseBlock(PredLoadI->getParent());
}
LoadI->replaceAllUsesWith(PN);
diff --git a/llvm/test/Transforms/JumpThreading/invalidate-lvi.ll b/llvm/test/Transforms/JumpThreading/invalidate-lvi.ll
index 9c5cbfac62d9fb5..27191d6f54c2d8c 100644
--- a/llvm/test/Transforms/JumpThreading/invalidate-lvi.ll
+++ b/llvm/test/Transforms/JumpThreading/invalidate-lvi.ll
@@ -12,15 +12,21 @@ define void @foo(i1 %0) {
; CHECK-NEXT: [[V:%.*]] = alloca i64, align 8
; CHECK-NEXT: call void @set_value(ptr [[V]])
; CHECK-NEXT: [[L1:%.*]] = load i64, ptr [[V]], align 8
-; CHECK-NEXT: br i1 [[TMP0]], label [[BB0:%.*]], label [[BB4:%.*]]
+; CHECK-NEXT: br i1 [[TMP0]], label [[BB0:%.*]], label [[BB2:%.*]]
; CHECK: bb0:
; CHECK-NEXT: [[C1:%.*]] = icmp eq i64 [[L1]], 0
-; CHECK-NEXT: br i1 [[C1]], label [[BB1:%.*]], label [[BB4]]
-; CHECK: bb1:
+; CHECK-NEXT: br i1 [[C1]], label [[BB2_THREAD:%.*]], label [[BB2]]
+; CHECK: bb2.thread:
; CHECK-NEXT: store i64 0, ptr [[V]], align 8
-; CHECK-NEXT: br label [[BB4]]
+; CHECK-NEXT: br label [[BB4:%.*]]
+; CHECK: bb2:
+; CHECK-NEXT: [[L2:%.*]] = phi i64 [ [[L1]], [[BB0]] ], [ [[L1]], [[START:%.*]] ]
+; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i64 [[L2]], 2
+; CHECK-NEXT: br i1 [[TMP1]], label [[BB3:%.*]], label [[BB4]]
+; CHECK: bb3:
+; CHECK-NEXT: call void @bar()
+; CHECK-NEXT: ret void
; CHECK: bb4:
-; CHECK-NEXT: [[L2:%.*]] = phi i64 [ 0, [[BB1]] ], [ [[L1]], [[BB0]] ], [ [[L1]], [[START:%.*]] ]
; CHECK-NEXT: ret void
;
start:
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