[PATCH] D159301: [RISCV][llvm-mca] Fix getLMUL values

[Michael Maitland via Phabricator via llvm-commits]

michaelmaitland updated this revision to Diff 555510.
michaelmaitland added a comment.
Herald added a subscriber: gbedwell.

I've added a simple test. I plan on removing this test in the future with a set
of tests that shows behavior all instructions for all different LMUL and SEW
pairs.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D159301/new/

https://reviews.llvm.org/D159301

Files:
  llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp
  llvm/test/tools/llvm-mca/RISCV/fractional-lmul-data.s


Index: llvm/test/tools/llvm-mca/RISCV/fractional-lmul-data.s
===================================================================
--- /dev/null
+++ llvm/test/tools/llvm-mca/RISCV/fractional-lmul-data.s
@@ -0,0 +1,55 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -iterations=1 < %s | FileCheck %s
+
+# TODO: This test should be replaced by an exhaustive test of legal (LMUL, SEW)
+# pairs for all instructions in the Vector Integer Arithmetic chapter of the RVV
+# SPEC.
+vsetvli zero, zero, e32, mf2, tu, mu
+vdiv.vv v12, v12, v12
+vsetvli zero, zero, e8, mf8, tu, mu
+vdiv.vv v12, v12, v12
+
+# CHECK:      Iterations:        1
+# CHECK-NEXT: Instructions:      4
+# CHECK-NEXT: Total Cycles:      90
+# CHECK-NEXT: Total uOps:        4
+
+# CHECK:      Dispatch Width:    2
+# CHECK-NEXT: uOps Per Cycle:    0.04
+# CHECK-NEXT: IPC:               0.04
+# CHECK-NEXT: Block RThroughput: 86.0
+
+# CHECK:      Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
+# CHECK-NEXT:  1      3     1.00                  U     vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  1      56    56.00                       vdiv.vv	v12, v12, v12
+# CHECK-NEXT:  1      3     1.00                  U     vsetvli	zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT:  1      30    30.00                       vdiv.vv	v12, v12, v12
+
+# CHECK:      Resources:
+# CHECK-NEXT: [0]   - SiFive7FDiv
+# CHECK-NEXT: [1]   - SiFive7IDiv
+# CHECK-NEXT: [2]   - SiFive7PipeA
+# CHECK-NEXT: [3]   - SiFive7PipeB
+# CHECK-NEXT: [4]   - SiFive7PipeV
+# CHECK-NEXT: [5]   - SiFive7VA
+# CHECK-NEXT: [6]   - SiFive7VL
+# CHECK-NEXT: [7]   - SiFive7VS
+
+# CHECK:      Resource pressure per iteration:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]
+# CHECK-NEXT:  -      -     2.00    -     86.00  86.00   -      -
+
+# CHECK:      Resource pressure by instruction:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    Instructions:
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -     vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -     56.00  56.00   -      -     vdiv.vv	v12, v12, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -     vsetvli	zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT:  -      -      -      -     30.00  30.00   -      -     vdiv.vv	v12, v12, v12
Index: llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp
===================================================================
--- llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp
+++ llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp
@@ -63,9 +63,9 @@
       .Case("M2", 0b001)
       .Case("M4", 0b010)
       .Case("M8", 0b011)
-      .Case("MF2", 0b101)
+      .Case("MF2", 0b111)
       .Case("MF4", 0b110)
-      .Case("MF8", 0b111);
+      .Case("MF8", 0b101);
 }
 
 const llvm::StringRef RISCVSEWInstrument::DESC_NAME = "RISCV-SEW";


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