[llvm] 3c8bb18 - [AArch64][SME] Don't use OBSCURE_COPY to avoid rematerialization.
Sander de Smalen via llvm-commits
llvm-commits at lists.llvm.org
Fri Sep 1 06:36:50 PDT 2023
Author: Sander de Smalen
Date: 2023-09-01T13:36:03Z
New Revision: 3c8bb18162335c753ae54ff962ca5e91eab50fbc
URL: https://github.com/llvm/llvm-project/commit/3c8bb18162335c753ae54ff962ca5e91eab50fbc
DIFF: https://github.com/llvm/llvm-project/commit/3c8bb18162335c753ae54ff962ca5e91eab50fbc.diff
LOG: [AArch64][SME] Don't use OBSCURE_COPY to avoid rematerialization.
This is intended to be a non-functional change. This patch removes
OBSCURE_COPY in favour of using `forceDisableTriviallyReMaterializable`.
Reviewed By: paulwalker-arm
Differential Revision: https://reviews.llvm.org/D159194
Added:
Modified:
llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.h
llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp b/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
index d2684fe8b3348c..fbac23f63face6 100644
--- a/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
@@ -1515,17 +1515,6 @@ bool AArch64ExpandPseudo::expandMI(MachineBasicBlock &MBB,
NextMBBI = MBB.end(); // The NextMBBI iterator is invalidated.
return true;
}
- case AArch64::OBSCURE_COPY: {
- if (MI.getOperand(0).getReg() != MI.getOperand(1).getReg()) {
- BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ORRXrs))
- .add(MI.getOperand(0))
- .addReg(AArch64::XZR)
- .add(MI.getOperand(1))
- .addImm(0);
- }
- MI.eraseFromParent();
- return true;
- }
case AArch64::LD1B_2Z_IMM_PSEUDO:
return expandMultiVecPseudo(
MBB, MBBI, AArch64::ZPR2RegClass, AArch64::ZPR2StridedRegClass,
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 33d9beed41ff00..0c8432daeb8c56 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -2303,7 +2303,6 @@ const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {
switch ((AArch64ISD::NodeType)Opcode) {
case AArch64ISD::FIRST_NUMBER:
break;
- MAKE_CASE(AArch64ISD::OBSCURE_COPY)
MAKE_CASE(AArch64ISD::SMSTART)
MAKE_CASE(AArch64ISD::SMSTOP)
MAKE_CASE(AArch64ISD::RESTORE_ZA)
@@ -7510,11 +7509,6 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
return ArgReg.Reg == VA.getLocReg();
});
} else {
- // Add an extra level of indirection for streaming mode changes by
- // using a pseudo copy node that cannot be rematerialised between a
- // smstart/smstop and the call by the simple register coalescer.
- if (RequiresSMChange && isa<FrameIndexSDNode>(Arg))
- Arg = DAG.getNode(AArch64ISD::OBSCURE_COPY, DL, MVT::i64, Arg);
RegsToPass.emplace_back(VA.getLocReg(), Arg);
RegsUsed.insert(VA.getLocReg());
const TargetOptions &Options = DAG.getTarget().Options;
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
index bce030de226b83..6e92b2fcab0756 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
@@ -58,13 +58,6 @@ enum NodeType : unsigned {
CALL_BTI, // Function call followed by a BTI instruction.
- // Essentially like a normal COPY that works on GPRs, but cannot be
- // rematerialised by passes like the simple register coalescer. It's
- // required for SME when lowering calls because we cannot allow frame
- // index calculations using addvl to slip in between the smstart/smstop
- // and the bl instruction. The scalable vector length may change across
- // the smstart/smstop boundary.
- OBSCURE_COPY,
SMSTART,
SMSTOP,
RESTORE_ZA,
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index 33a6906b0a0d3c..72c791af4b43b0 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -8538,7 +8538,11 @@ bool AArch64InstrInfo::isReallyTriviallyReMaterializable(
// scalable values, such as 'pfalse' or 'ptrue', which result in
diff erent
// results when the runtime vector length is
diff erent.
const MachineRegisterInfo &MRI = MF.getRegInfo();
- if (any_of(MI.operands(), [&MRI](const MachineOperand &MO) {
+ const MachineFrameInfo &MFI = MF.getFrameInfo();
+ if (any_of(MI.operands(), [&MRI, &MFI](const MachineOperand &MO) {
+ if (MO.isFI() &&
+ MFI.getStackID(MO.getIndex()) == TargetStackID::ScalableVector)
+ return true;
if (!MO.isReg())
return false;
diff --git a/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
index 352f34cab132ad..f306021dd75335 100644
--- a/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
@@ -23,8 +23,6 @@ def AArch64_restore_za : SDNode<"AArch64ISD::RESTORE_ZA", SDTypeProfile<0, 3,
[SDNPHasChain, SDNPSideEffect, SDNPVariadic,
SDNPOptInGlue]>;
-def AArch64ObscureCopy : SDNode<"AArch64ISD::OBSCURE_COPY", SDTypeProfile<1, 1, []>, []>;
-
//===----------------------------------------------------------------------===//
// Instruction naming conventions.
//===----------------------------------------------------------------------===//
@@ -185,10 +183,6 @@ def : Pat<(int_aarch64_sme_set_tpidr2 i64:$val),
(MSR 0xde85, GPR64:$val)>;
def : Pat<(i64 (int_aarch64_sme_get_tpidr2)),
(MRS 0xde85)>;
-
-def OBSCURE_COPY : Pseudo<(outs GPR64:$dst), (ins GPR64:$idx), []>, Sched<[]> { }
-def : Pat<(i64 (AArch64ObscureCopy (i64 GPR64:$idx))),
- (OBSCURE_COPY GPR64:$idx)>;
} // End let Predicates = [HasSME]
// Pseudo to match to smstart/smstop. This expands:
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