[PATCH] D158364: [DAG] SimplifyDemandedBits - if we're only demanding the signbits, a MIN/MAX node can be simplified to a OR or AND node

[Simon Pilgrim via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGaca8b9d0d56e: [DAG] SimplifyDemandedBits - if we're only demanding the signbits, a MIN/MAX… (authored by RKSimon).

Changed prior to commit:
  https://reviews.llvm.org/D158364?vs=553432&id=555316#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D158364/new/

https://reviews.llvm.org/D158364

Files:
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/test/CodeGen/X86/known-signbits-vector.ll

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