[PATCH] D154488: [PowerPC] Define SchedModel for Power8

[Qiu Chaofan via Phabricator via llvm-commits]

qiucf added inline comments.


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Comment at: llvm/lib/Target/PowerPC/PPCScheduleP8.td:169
+  def : InstRW<[P8_LS_FP_FX_2C, P8_ISSUE_ST], (instrs STVEBX, STVEHX, STVEWX, STVX, STVXL)>;
+  def : InstRW<[P8_LS_FP_FX_3C, P8_ISSUE_ST], (instregex "^STF(D|S)U(X)?$")>;
+  def : InstRW<[P8_LS_FX_3C, P8_ISSUE_FXLD], (instrs LQ)>;
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shchenz wrote:
> For cracked instructions, should we only use one issue port?
I tried modelling cracked instructions, but not got good performance results, which can be future improvement item. I added a `TODO` note.


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Comment at: llvm/lib/Target/PowerPC/PPCScheduleP8.td:171
+  def : InstRW<[P8_LS_FX_3C, P8_ISSUE_FXLD], (instrs LQ)>;
+  def : InstRW<[P8_LU_2C, P8_ISSUE_FXLD], (instregex "^(ADD|SUBF|NEG)(4|8)?_rec$")>;
+  def : InstRW<[P8_LU_FX_5C, P8_ISSUE_LD], (instregex "^LF(D|S)U(X)?$")>;
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shchenz wrote:
> ADD_rec/SUBF_rec/NEG_rec seems can use both FXU or LSU?
Thanks, moved to use only FX instead.


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  https://reviews.llvm.org/D154488/new/

https://reviews.llvm.org/D154488