[PATCH] D156444: [llvm][RISCV][IR] Zext flag in IR for RISC-V

[Panagiotis K via Phabricator via llvm-commits]

karouzakisp added a comment.

In D156444#4632536 <https://reviews.llvm.org/D156444#4632536>, @craig.topper wrote:

> In D156444#4632497 <https://reviews.llvm.org/D156444#4632497>, @karouzakisp wrote:
>
>> In D156444#4624088 <https://reviews.llvm.org/D156444#4624088>, @nikic wrote:
>>
>>> This is still missing LangRef changes.
>>>
>>> I think you should also drop everything here that is related to supporting zext constant expressions. These will be removed in the near future, and I don't think it makes sense to add nneg support for them just to drop them again.
>>
>> "
>> Semantics:
>>
>> The zext fills the high order bits of the value with zero bits until it reaches the size of the destination type, ty2.
>>
>> When zero extending from i1, the result will always be either 0 or 1.
>>
>> The nneg flag means the value to be zero extended is non negative.
>> So we can safely convert the zext to a sext.
>> This applies only for the RISC-V target because sext i32 to i64 can be a no op for RV64
>> and it is always cheaper than performing a zero extension .
>>
>> Example:
>> %X = zext i32 257 to i64              ; yields i64:257
>> %Y = zext i1 true to i32              ; yields i32:1
>> %Z = zext <2 x i16> <i16 8, i16 7> to <2 x i32> ; yields <i32 8, i32 7>
>> %H = zext nneg 8 i32 to i64        ; yields to i64:8
>
> I don't think we need to mention RISC-V. I've seen cases where the middle end needs this information. This issue https://discourse.llvm.org/t/aggressive-conversion-of-sext-to-zext-blocks-indvarsimplify/61561 was independent of RISC-V.

Semantics:

The zext fills the high order bits of the value with zero bits until it reaches the size of the destination type, ty2.

When zero extending from i1, the result will always be either 0 or 1.

The nneg flag means the value to be zero extended is non negative.
So we can safely convert the zext to a sext.

Example:
%X = zext i32 257 to i64 ; yields i64:257
%Y = zext i1 true to i32 ; yields i32:1
%Z = zext <2 x i16> <i16 8, i16 7> to <2 x i32> ; yields <i32 8, i32 7>
%H = zext nneg 8 i32 to i64 ; yields to i64:8


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