[PATCH] D159306: [RISCV] Remove XLen field from RISCVSubtarget [nfc]

[Philip Reames via Phabricator via llvm-commits]

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We also have IsRV64 which, unless I'm missing something, contains the same information.  I did add an assert to catch the case where the triple and cpu are out of sync.  I haven't checked, but I assume a more useful error is reported by clang.  Or at least, I can't think of a configuration where a rv32 triple and a rv64 cpu definition (and thus ISEL) make sense.  Posting this for review mostly to make sure I'm not missing something on that point.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D159306

Files:
  llvm/lib/Target/RISCV/RISCVSubtarget.cpp
  llvm/lib/Target/RISCV/RISCVSubtarget.h


Index: llvm/lib/Target/RISCV/RISCVSubtarget.h
===================================================================
--- llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -48,7 +48,6 @@
   bool ATTRIBUTE = DEFAULT;
 #include "RISCVGenSubtargetInfo.inc"
 
-  unsigned XLen = 32;
   unsigned ZvlLen = 0;
   unsigned RVVVectorBitsMin;
   unsigned RVVVectorBitsMax;
@@ -127,12 +126,10 @@
   }
   bool is64Bit() const { return IsRV64; }
   MVT getXLenVT() const {
-    return MVT::getIntegerVT(getXLen());
+    return is64Bit() ? MVT::i64 : MVT::i32;
   }
   unsigned getXLen() const {
-    assert((XLen == 32 || XLen == 64) &&
-           "unexpected xlen");
-    return XLen;
+    return is64Bit() ? 64 : 32;
   }
   unsigned getFLen() const {
     if (HasStdExtD)
Index: llvm/lib/Target/RISCV/RISCVSubtarget.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVSubtarget.cpp
+++ llvm/lib/Target/RISCV/RISCVSubtarget.cpp
@@ -66,8 +66,7 @@
     TuneCPU = CPU;
 
   ParseSubtargetFeatures(CPU, TuneCPU, FS);
-  if (Is64Bit)
-    XLen = 64;
+  assert(Is64Bit == IsRV64 && "unexpected triple/cpu mismatch");
 
   TargetABI = RISCVABI::computeTargetABI(TT, getFeatureBits(), ABIName);
   RISCVFeatures::validate(TT, getFeatureBits());


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