[llvm] 1664eb0 - [RISCV] Fix crash during during i1 vector bitreverse lowering

[Luke Lau via llvm-commits]

Author: Luke Lau
Date: 2023-08-31T19:39:08+01:00
New Revision: 1664eb05d0d335c7624e463d391beae8e32d74ba

URL: https://github.com/llvm/llvm-project/commit/1664eb05d0d335c7624e463d391beae8e32d74ba
DIFF: https://github.com/llvm/llvm-project/commit/1664eb05d0d335c7624e463d391beae8e32d74ba.diff

LOG: [RISCV] Fix crash during during i1 vector bitreverse lowering

A shuffle of v256i1 with a large enough minimum vlen might make it through type
legalization and into lowering. In this case, zvl1024b was enough. The
bitreverse shuffle lowering would then try to convert this to a v1i256 type
which is invalid (v1i128 exists though, which is why the existing v128i1 tests
were fine).

This patch checks to make sure that the new type is not only legal but also
valid.

Reviewed By: craig.topper, reames

Differential Revision: https://reviews.llvm.org/D159215

Added: 
    llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse-bitrotate.ll

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 817cef88d85649..9abc68921c48ae 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -4191,13 +4191,16 @@ static SDValue lowerBitreverseShuffle(ShuffleVectorSDNode *SVN,
     return SDValue();
 
   unsigned ViaEltSize = std::max((uint64_t)8, PowerOf2Ceil(NumElts));
-  MVT ViaVT = MVT::getVectorVT(MVT::getIntegerVT(ViaEltSize), 1);
-  MVT ViaBitVT = MVT::getVectorVT(MVT::i1, ViaVT.getScalarSizeInBits());
+  EVT ViaVT = EVT::getVectorVT(
+      *DAG.getContext(), EVT::getIntegerVT(*DAG.getContext(), ViaEltSize), 1);
+  EVT ViaBitVT =
+      EVT::getVectorVT(*DAG.getContext(), MVT::i1, ViaVT.getScalarSizeInBits());
 
   // If we don't have zvbb or the larger element type > ELEN, the operation will
   // be illegal.
   if (!Subtarget.getTargetLowering()->isOperationLegalOrCustom(ISD::BITREVERSE,
-                                                               ViaVT))
+                                                               ViaVT) ||
+      !Subtarget.getTargetLowering()->isTypeLegal(ViaBitVT))
     return SDValue();
 
   // If the bit vector doesn't fit exactly into the larger element type, we need

diff  --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse-bitrotate.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse-bitrotate.ll
new file mode 100644
index 00000000000000..d4c0477408fd66
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse-bitrotate.ll
@@ -0,0 +1,23 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
+; RUN: llc -mtriple=riscv32 -mattr=+v,+zvl1024b -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zvl1024b -verify-machineinstrs < %s | FileCheck %s
+
+; There is no corresponding v1i256 type, so make sure we don't crash if we try
+; to lower via lowerBitreverseShuffle.
+define <256 x i1> @reverse_v256i1(<256 x i1> %a) {
+; CHECK-LABEL: reverse_v256i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, 256
+; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma
+; CHECK-NEXT:    vmv.v.i v8, 0
+; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
+; CHECK-NEXT:    vid.v v10
+; CHECK-NEXT:    vrsub.vi v10, v10, -1
+; CHECK-NEXT:    vrgather.vv v12, v8, v10
+; CHECK-NEXT:    vmsne.vi v0, v12, 0
+; CHECK-NEXT:    ret
+  %res = call <256 x i1> @llvm.experimental.vector.reverse.v256i1(<256 x i1> %a)
+  ret <256 x i1> %res
+}
+
+declare <256 x i1> @llvm.experimental.vector.reverse.v256i1(<256 x i1>)