[PATCH] D158853: [SDAG] Add SimplifyDemandedBits support for ISD::SPLAT_VECTOR_PARTS

[Luke Lau via Phabricator via llvm-commits]

luke added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/rvv/splat-vector-split-i64-vl-sdnode.ll:117
 ; CHECK-NEXT:    sw a1, 4(sp)
 ; CHECK-NEXT:    sw a0, 0(sp)
 ; CHECK-NEXT:    mv a0, sp
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This a0 is actually undef, it's just selected by coincidence because there's no combine after RISCVDAGToDAGISel::PreprocessISelDAG to remove the store of undef. Might it be worthwhile short-circuiting a store of undef directly in SelectionDAG::getStore?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D158853/new/

https://reviews.llvm.org/D158853