[PATCH] D158364: [DAG] SimplifyDemandedBits - if we're only demanding the signbits, a MIN/MAX node can be simplified to a OR or AND node

[Noah Goldstein via Phabricator via llvm-commits]

goldstein.w.n added a comment.

Other than the few nits looks good.



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Comment at: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:2161
+    case ISD::SMAX:
+      // TODO: Add KnownBits::sge/sgt handling.
+      break;
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Should compute Known for `smin`/`smax`? Imo also just fill in the TODO. Its not much code required.


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Comment at: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:2171
+    case ISD::UMAX:
+      Known = KnownBits::umax(Known0, Known1);
+      if (std::optional<bool> IsUGE = KnownBits::uge(Known0, Known1))
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I guess already existed but Known computation should be after the condition folding has failed already.


Repository:
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  https://reviews.llvm.org/D158364/new/

https://reviews.llvm.org/D158364