[PATCH] D159254: [AArch64] Fix schedmodel pre/post-index loads and stores for Neoverse V2

[Sjoerd Meijer via Phabricator via llvm-commits]

SjoerdMeijer added a comment.

Thanks for taking a look!

> Are there any that test the loaded latency, not the index update?
>
> ldr  x1, [x27], #254
> ldr  x2, [x1], #254

I have added this test. Test file `V2-writeback.s` is a new one. I have precommitted that locally, to only show the differences here.

With your test case added, and this patch applied, there is no difference before/after. In other words, the behaviour is not changed, which I think is what you wanted to check:

  CHECK:      [0,0]     DeeeeER   .   ldr       x1, [x27], #254
  CHECK-NEXT: [0,1]     D====eeeeER   ldr       x2, [x1], #254



================
Comment at: llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td:1367
 // Load vector pair, immed pre-index, Q-form
-def : InstRW<[V2Write_6cyc_2I_2L, WriteLDHi, WriteAdr], (instrs LDPQpost,
+def : InstRW<[WriteAdr, V2Write_6cyc_2I_2L, WriteLDHi], (instrs LDPQpost,
                                                                 LDPQpre)>;
----------------
david-arm wrote:
> This seems to be matching both pre- and post- forms. Same with the change above. Does that matter?
Another way of looking at this is that this is a correctness fix: the first operand is the update/increment. By fixing that, the correct performance behaviour just falls out from that. And yes, I think doing this for the pre- and post- forms is what we want.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D159254/new/

https://reviews.llvm.org/D159254