[PATCH] D159266: [BOLT] Provide generic implementations for isLoad/isStore

[Job Noorman via Phabricator via llvm-commits]

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`MCInstrDesc` provides the `mayLoad` and `mayStore` flags that seem
appropriate to use as a target-independent way to implement `isLoad` and
`isStore`.

I believe this is currently good enough to use for the RISC-V target as
well. I've provided a test for this that checks the generated dyno
stats (which seems to be the only thing both `isLoad` and `isStore` are
used for).


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D159266

Files:
  bolt/include/bolt/Core/MCPlusBuilder.h
  bolt/test/RISCV/load-store.s


Index: bolt/test/RISCV/load-store.s
===================================================================
--- /dev/null
+++ bolt/test/RISCV/load-store.s
@@ -0,0 +1,16 @@
+// RUN: %clang %cflags -o %t %s
+// RUN: link_fdata --no-lbr %s %t %t.fdata
+// RUN: llvm-bolt %t -o /dev/null -data=%t.fdata -dyno-stats | FileCheck %s
+
+// CHECK: BOLT-INFO: program-wide dynostats after all optimizations before SCTC and FOP (no change):
+// CHECK: 3000 : executed instructions
+// CHECK: 1000 : executed load instructions
+// CHECK: 1000 : executed store instructions
+
+    .globl _start
+_start:
+# FDATA: 1 _start #_start# 1
+    ld t0, (gp)
+    sd t0, (gp)
+    ret
+    .size _start, .-_start
Index: bolt/include/bolt/Core/MCPlusBuilder.h
===================================================================
--- bolt/include/bolt/Core/MCPlusBuilder.h
+++ bolt/include/bolt/Core/MCPlusBuilder.h
@@ -614,13 +614,11 @@
   virtual bool isMoveMem2Reg(const MCInst &Inst) const { return false; }
 
   virtual bool isLoad(const MCInst &Inst) const {
-    llvm_unreachable("not implemented");
-    return false;
+    return Info->get(Inst.getOpcode()).mayLoad();
   }
 
   virtual bool isStore(const MCInst &Inst) const {
-    llvm_unreachable("not implemented");
-    return false;
+    return Info->get(Inst.getOpcode()).mayStore();
   }
 
   virtual bool isCleanRegXOR(const MCInst &Inst) const {


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