[PATCH] D159265: [AArch64] Remove copy instruction between uaddlv and urshr

[JinGu Kang via Phabricator via llvm-commits]

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gcc generates less number of instructions from below example than llvm.

  #include <arm_neon.h>
  
  uint8x8_t foo(uint8x8_t a) {
      return vdup_n_u8(vrshrd_n_u64(vaddlv_u8(a), 3));
  }
  
  gcc output
  foo:
          uaddlv  h0, v0.8b
          urshr   d0, d0, 3
          dup     v0.8b, v0.b[0]
          ret
  
  llvm output
  foo:
          uaddlv  h0, v0.8b
          fmov    w8, s0
          fmov    d0, x8
          urshr   d0, d0, #3
          dup     v0.8b, v0.b[0]
          ret

There are copy instructions between gpr and fpr. We could remove them as below pattern.

  def : Pat<(v1i64 (scalar_to_vector (i64 (zext (i32 (int_aarch64_neon_uaddlv (v8i8 V64:$Rn))))))),
            (INSERT_SUBREG (v1i64 (IMPLICIT_DEF)), (UADDLVv8i8v V64:$Rn), hsub)>;

With above pattern, llvm generates below output.

  foo:                                    // @foo
          uaddlv  h0, v0.8b
          urshr   d0, d0, #3
          dup     v0.8b, v0.b[0]
          ret

The pattern could be too specific for this example. If you have other idea to generalize this case, please let me know.


https://reviews.llvm.org/D159265

Files:
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/test/CodeGen/AArch64/neon-addlv.ll


Index: llvm/test/CodeGen/AArch64/neon-addlv.ll
===================================================================
--- llvm/test/CodeGen/AArch64/neon-addlv.ll
+++ llvm/test/CodeGen/AArch64/neon-addlv.ll
@@ -177,3 +177,23 @@
   %0 = and i32 %vaddlv.i, 65535
   ret i32 %0
 }
+
+declare i64 @llvm.aarch64.neon.urshl.i64(i64, i64)
+
+define <8 x i8> @foo(<8 x i8> noundef %a) {
+; CHECK-LABEL: foo:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    uaddlv h0, v0.8b
+; CHECK-NEXT:    urshr d0, d0, #3
+; CHECK-NEXT:    dup v0.8b, v0.b[0]
+; CHECK-NEXT:    ret
+entry:
+  %vaddlv.i = tail call i32 @llvm.aarch64.neon.uaddlv.i32.v8i8(<8 x i8> %a)
+  %0 = and i32 %vaddlv.i, 65535
+  %conv = zext i32 %0 to i64
+  %vrshr_n = tail call i64 @llvm.aarch64.neon.urshl.i64(i64 %conv, i64 -3)
+  %conv1 = trunc i64 %vrshr_n to i8
+  %vecinit.i = insertelement <8 x i8> undef, i8 %conv1, i64 0
+  %vecinit7.i = shufflevector <8 x i8> %vecinit.i, <8 x i8> poison, <8 x i32> zeroinitializer
+  ret <8 x i8> %vecinit7.i
+}
Index: llvm/lib/Target/AArch64/AArch64InstrInfo.td
===================================================================
--- llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -6427,6 +6427,9 @@
 defm FMINNMV : SIMDFPAcrossLanes<0b01100, 1, "fminnmv", AArch64fminnmv>;
 defm FMINV   : SIMDFPAcrossLanes<0b01111, 1, "fminv", AArch64fminv>;
 
+def : Pat<(v1i64 (scalar_to_vector (i64 (zext (i32 (int_aarch64_neon_uaddlv (v8i8 V64:$Rn))))))),
+          (SUBREG_TO_REG (i64 0), (UADDLVv8i8v V64:$Rn), hsub)>;
+
 multiclass SIMDAcrossLaneLongPairIntrinsic<string Opc, SDPatternOperator addlp> {
   // Patterns for addv(addlp(x)) ==> addlv
   def : Pat<(i32 (vector_extract (v8i16 (insert_subvector undef,


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