[PATCH] D159215: [RISCV] Fix crash during during i1 vector bitreverse lowering

[Luke Lau via Phabricator via llvm-commits]

luke added a comment.

In D159215#4630041 <https://reviews.llvm.org/D159215#4630041>, @wangpc wrote:

> I was thinking about adding `v1i256`, `v1i512`, etc. Is it feasible?

I've updated the diff to use EVTs as per Craig's suggestion, it should be ok if any larger types are added now.



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Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll:5
 ; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+f,+d,+zfh,+zvfh -riscv-v-vector-bits-max=512 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,NO-ZVBB,RV32-BITS-512
+; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+f,+d,+zfh,+zvfh -riscv-v-vector-bits-max=1024 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,NO-ZVBB,RV32-BITS-1024
 ; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zfh,+zvfh -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,NO-ZVBB,RV64-BITS-UNKNOWN
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craig.topper wrote:
> This is the wrong command line for the bug. Don't you need +zvl256b? The bug is due to the min vlen, not the max vlen.
Yeah, not sure what I was thinking. 


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https://reviews.llvm.org/D159215