[PATCH] D159253: [RISCV] Teach MatInt to use (ADD_UW X, (SLLI X, 32)) to materialize some constants.

[Craig Topper via Phabricator via llvm-commits]

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If the high and low 32 bits are the same, we try to use
(ADD X, (SLLI X, 32)) but that only works if bit 31 is clear since
the low 32 bits will be sign extended.

If we have Zba we can use add.uw to zero the sign extended bits.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D159253

Files:
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/imm.ll

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