[PATCH] D159215: [RISCV] Fix crash during during i1 vector bitreverse lowering

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:4230
   unsigned ViaEltSize = std::max((uint64_t)8, PowerOf2Ceil(NumElts));
   MVT ViaVT = MVT::getVectorVT(MVT::getIntegerVT(ViaEltSize), 1);
+  if (!ViaVT.isValid())
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Can we use `EVT ViaVT = EVT::getVectorVT(*DAG.getContext(), EVT::getIntegerVT(*DAG.getContext(), ViaEltSize), 1);` so we're not trying to create non-existent MVTs?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D159215/new/

https://reviews.llvm.org/D159215