[PATCH] D154488: [PowerPC] Define SchedModel for Power8

[ChenZheng via Phabricator via llvm-commits]

shchenz added a comment.

Looks almost good to me. Some other comments related to the instruction definitions.

Please note the two failures in the premerge check on X86 target.



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Comment at: llvm/lib/Target/PowerPC/PPCScheduleP8.td:68
+  // Two ports for fixed-point operations.
+  def P8_PORT_FX : ProcResource<2> { let Super = P8_PORT_ALLFX; }
+  // Two issue ports shared by two floating-point, two VSX, two VMX, one crypto,
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nit: This issue port is not used?


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Comment at: llvm/lib/Target/PowerPC/PPCScheduleP8.td:88
+  def P8_LS_LU : SchedWriteRes<[P8_LU, P8_LS]>;
+  def P8_LS_FP : SchedWriteRes<[P8_LU, P8_FPU]>;
+  def P8_LU_LS_3C : SchedWriteRes<[P8_LU_LS]> { let Latency = 3; }
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should be `def P8_LS_FP : SchedWriteRes<[P8_LSU, P8_FPU]>;`?


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Comment at: llvm/lib/Target/PowerPC/PPCScheduleP8.td:169
+  def : InstRW<[P8_LS_FP_FX_2C, P8_ISSUE_ST], (instrs STVEBX, STVEHX, STVEWX, STVX, STVXL)>;
+  def : InstRW<[P8_LS_FP_FX_3C, P8_ISSUE_ST], (instregex "^STF(D|S)U(X)?$")>;
+  def : InstRW<[P8_LS_FX_3C, P8_ISSUE_FXLD], (instrs LQ)>;
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For cracked instructions, should we only use one issue port?


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Comment at: llvm/lib/Target/PowerPC/PPCScheduleP8.td:171
+  def : InstRW<[P8_LS_FX_3C, P8_ISSUE_FXLD], (instrs LQ)>;
+  def : InstRW<[P8_LU_2C, P8_ISSUE_FXLD], (instregex "^(ADD|SUBF|NEG)(4|8)?_rec$")>;
+  def : InstRW<[P8_LU_FX_5C, P8_ISSUE_LD], (instregex "^LF(D|S)U(X)?$")>;
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ADD_rec/SUBF_rec/NEG_rec seems can use both FXU or LSU?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D154488/new/

https://reviews.llvm.org/D154488