[llvm] 079c968 - [RISCV] Form vmv.s.f/x from single element splats via DAG combine
Philip Reames via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 30 12:44:57 PDT 2023
Author: Philip Reames
Date: 2023-08-30T12:44:36-07:00
New Revision: 079c968eb95aa2c84444d0e5d5564d575b93c909
URL: https://github.com/llvm/llvm-project/commit/079c968eb95aa2c84444d0e5d5564d575b93c909
DIFF: https://github.com/llvm/llvm-project/commit/079c968eb95aa2c84444d0e5d5564d575b93c909.diff
LOG: [RISCV] Form vmv.s.f/x from single element splats via DAG combine
This re-implements the special casing we had in lowerScalarSplat as a DAG combine. As can be seen in the tests, this ends up triggering in a bunch more cases.
The semantically interesting bit of this change is the use of the implicit truncate semantics for when XLEN > SEW. We'd already been doing this for vmv.v.x, but this change extends e.g. the constant matching to make the same assumption about vmv.s.x. Per my reading of the specification, this should be fine, and if anything, is more obviously true of vmv.s.x than vmv.v.x.
Differential Revision: https://reviews.llvm.org/D158874
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-deinterleave-load.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-i1.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access-zve32x.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-int.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-transpose.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store-asm.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfcmp-constrained-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfcmps-constrained-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmacc.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vitofp-constrained-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrol.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vror.ll
llvm/test/CodeGen/RISCV/rvv/shuffle-reverse.ll
llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 2f8d8d9106aaef..03f5f43dabb215 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -2957,7 +2957,8 @@ bool RISCVDAGToDAGISel::selectVLOp(SDValue N, SDValue &VL) {
static SDValue findVSplat(SDValue N) {
SDValue Splat = N;
- if (Splat.getOpcode() != RISCVISD::VMV_V_X_VL ||
+ if ((Splat.getOpcode() != RISCVISD::VMV_V_X_VL &&
+ Splat.getOpcode() != RISCVISD::VMV_S_X_VL) ||
!Splat.getOperand(0).isUndef())
return SDValue();
assert(Splat.getNumOperands() == 3 && "Unexpected number of operands");
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 7d177b26efb4e0..6a4995ea96b26d 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -3622,12 +3622,8 @@ static SDValue lowerScalarSplat(SDValue Passthru, SDValue Scalar, SDValue VL,
bool HasPassthru = Passthru && !Passthru.isUndef();
if (!HasPassthru && !Passthru)
Passthru = DAG.getUNDEF(VT);
- if (VT.isFloatingPoint()) {
- // If VL is 1, we could use vfmv.s.f.
- if (isOneConstant(VL))
- return DAG.getNode(RISCVISD::VFMV_S_F_VL, DL, VT, Passthru, Scalar, VL);
+ if (VT.isFloatingPoint())
return DAG.getNode(RISCVISD::VFMV_V_F_VL, DL, VT, Passthru, Scalar, VL);
- }
MVT XLenVT = Subtarget.getXLenVT();
@@ -3640,12 +3636,6 @@ static SDValue lowerScalarSplat(SDValue Passthru, SDValue Scalar, SDValue VL,
unsigned ExtOpc =
isa<ConstantSDNode>(Scalar) ? ISD::SIGN_EXTEND : ISD::ANY_EXTEND;
Scalar = DAG.getNode(ExtOpc, DL, XLenVT, Scalar);
- ConstantSDNode *Const = dyn_cast<ConstantSDNode>(Scalar);
- // If VL is 1 and the scalar value won't benefit from immediate, we could
- // use vmv.s.x.
- if (isOneConstant(VL) &&
- (!Const || isNullConstant(Scalar) || !isInt<5>(Const->getSExtValue())))
- return DAG.getNode(RISCVISD::VMV_S_X_VL, DL, VT, Passthru, Scalar, VL);
return DAG.getNode(RISCVISD::VMV_V_X_VL, DL, VT, Passthru, Scalar, VL);
}
@@ -13947,15 +13937,39 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
if (SDValue V = performCONCAT_VECTORSCombine(N, DAG, Subtarget, *this))
return V;
break;
+ case RISCVISD::VFMV_V_F_VL: {
+ const MVT VT = N->getSimpleValueType(0);
+ SDValue Passthru = N->getOperand(0);
+ SDValue Scalar = N->getOperand(1);
+ SDValue VL = N->getOperand(2);
+
+ // If VL is 1, we can use vfmv.s.f.
+ if (isOneConstant(VL))
+ return DAG.getNode(RISCVISD::VFMV_S_F_VL, DL, VT, Passthru, Scalar, VL);
+ break;
+ }
case RISCVISD::VMV_V_X_VL: {
+ const MVT VT = N->getSimpleValueType(0);
+ SDValue Passthru = N->getOperand(0);
+ SDValue Scalar = N->getOperand(1);
+ SDValue VL = N->getOperand(2);
+
// Tail agnostic VMV.V.X only demands the vector element bitwidth from the
// scalar input.
- unsigned ScalarSize = N->getOperand(1).getValueSizeInBits();
- unsigned EltWidth = N->getValueType(0).getScalarSizeInBits();
- if (ScalarSize > EltWidth && N->getOperand(0).isUndef())
+ unsigned ScalarSize = Scalar.getValueSizeInBits();
+ unsigned EltWidth = VT.getScalarSizeInBits();
+ if (ScalarSize > EltWidth && Passthru.isUndef())
if (SimplifyDemandedLowBitsHelper(1, EltWidth))
return SDValue(N, 0);
+ // If VL is 1 and the scalar value won't benefit from immediate, we can
+ // use vmv.s.x. Do this only if legal to avoid breaking i64 sext(i32)
+ // patterns on rv32..
+ ConstantSDNode *Const = dyn_cast<ConstantSDNode>(Scalar);
+ if (isOneConstant(VL) && EltWidth <= Subtarget.getXLen() &&
+ (!Const || Const->isZero() || !isInt<5>(Const->getSExtValue())))
+ return DAG.getNode(RISCVISD::VMV_S_X_VL, DL, VT, Passthru, Scalar, VL);
+
break;
}
case RISCVISD::VFMV_S_F_VL: {
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
index 77de87e8537eff..6d68e04987156e 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
@@ -1423,7 +1423,7 @@ foreach fvtiToFWti = AllWidenableFloatVectors in {
foreach fvti = AllFloatVectors in {
let Predicates = GetVTypePredicates<fvti>.Predicates in {
- def : Pat<(fvti.Vector (SplatFPOp fvti.ScalarRegClass:$rs1)),
+ def : Pat<(fvti.Vector (riscv_vfmv_v_f_vl undef, fvti.ScalarRegClass:$rs1, srcvalue)),
(!cast<Instruction>("PseudoVFMV_V_"#fvti.ScalarSuffix#"_"#fvti.LMul.MX)
(fvti.Vector (IMPLICIT_DEF)),
(fvti.Scalar fvti.ScalarRegClass:$rs1),
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
index 4f7789a4f24f6e..78b67e59082308 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
@@ -586,9 +586,10 @@ def Low8BitsSplatPat
def SelectFPImm : ComplexPattern<fAny, 1, "selectFPImm", [], [], 1>;
-// Ignore the vl operand.
-def SplatFPOp : PatFrag<(ops node:$op),
- (riscv_vfmv_v_f_vl undef, node:$op, srcvalue)>;
+// Ignore the vl operand on vmv_v_f, and vmv_s_f.
+def SplatFPOp : PatFrags<(ops node:$op),
+ [(riscv_vfmv_v_f_vl undef, node:$op, srcvalue),
+ (riscv_vfmv_s_f_vl undef, node:$op, srcvalue)]>;
def sew8simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<8>", []>;
def sew16simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<16>", []>;
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll
index 4320f827b27d4b..bfade7830d2c16 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll
@@ -436,70 +436,46 @@ define <1 x i16> @bitcast_i16_v1i16(i16 %a) {
; CHECK-LABEL: bitcast_i16_v1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; CHECK-NEXT: vmv.v.x v8, a0
+; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret
;
; ELEN32-LABEL: bitcast_i16_v1i16:
; ELEN32: # %bb.0:
; ELEN32-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
-; ELEN32-NEXT: vmv.v.x v8, a0
+; ELEN32-NEXT: vmv.s.x v8, a0
; ELEN32-NEXT: ret
%b = bitcast i16 %a to <1 x i16>
ret <1 x i16> %b
}
define <2 x i16> @bitcast_i32_v2i16(i32 %a) {
-; RV32-LABEL: bitcast_i32_v2i16:
-; RV32: # %bb.0:
-; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; RV32-NEXT: vmv.s.x v8, a0
-; RV32-NEXT: ret
-;
-; RV64-LABEL: bitcast_i32_v2i16:
-; RV64: # %bb.0:
-; RV64-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; RV64-NEXT: vmv.v.x v8, a0
-; RV64-NEXT: ret
-;
-; RV32ELEN32-LABEL: bitcast_i32_v2i16:
-; RV32ELEN32: # %bb.0:
-; RV32ELEN32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV32ELEN32-NEXT: vmv.s.x v8, a0
-; RV32ELEN32-NEXT: ret
+; CHECK-LABEL: bitcast_i32_v2i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
+; CHECK-NEXT: vmv.s.x v8, a0
+; CHECK-NEXT: ret
;
-; RV64ELEN32-LABEL: bitcast_i32_v2i16:
-; RV64ELEN32: # %bb.0:
-; RV64ELEN32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ELEN32-NEXT: vmv.v.x v8, a0
-; RV64ELEN32-NEXT: ret
+; ELEN32-LABEL: bitcast_i32_v2i16:
+; ELEN32: # %bb.0:
+; ELEN32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; ELEN32-NEXT: vmv.s.x v8, a0
+; ELEN32-NEXT: ret
%b = bitcast i32 %a to <2 x i16>
ret <2 x i16> %b
}
define <1 x i32> @bitcast_i32_v1i32(i32 %a) {
-; RV32-LABEL: bitcast_i32_v1i32:
-; RV32: # %bb.0:
-; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; RV32-NEXT: vmv.s.x v8, a0
-; RV32-NEXT: ret
-;
-; RV64-LABEL: bitcast_i32_v1i32:
-; RV64: # %bb.0:
-; RV64-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; RV64-NEXT: vmv.v.x v8, a0
-; RV64-NEXT: ret
-;
-; RV32ELEN32-LABEL: bitcast_i32_v1i32:
-; RV32ELEN32: # %bb.0:
-; RV32ELEN32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV32ELEN32-NEXT: vmv.s.x v8, a0
-; RV32ELEN32-NEXT: ret
+; CHECK-LABEL: bitcast_i32_v1i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
+; CHECK-NEXT: vmv.s.x v8, a0
+; CHECK-NEXT: ret
;
-; RV64ELEN32-LABEL: bitcast_i32_v1i32:
-; RV64ELEN32: # %bb.0:
-; RV64ELEN32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ELEN32-NEXT: vmv.v.x v8, a0
-; RV64ELEN32-NEXT: ret
+; ELEN32-LABEL: bitcast_i32_v1i32:
+; ELEN32: # %bb.0:
+; ELEN32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; ELEN32-NEXT: vmv.s.x v8, a0
+; ELEN32-NEXT: ret
%b = bitcast i32 %a to <1 x i32>
ret <1 x i32> %b
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-deinterleave-load.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-deinterleave-load.ll
index 713d2d2f40d356..3167bcf26837b6 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-deinterleave-load.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-deinterleave-load.ll
@@ -24,7 +24,7 @@ define {<16 x i1>, <16 x i1>} @vector_deinterleave_load_v16i1_v32i1(ptr %p) {
; RV32-NEXT: lui a0, 16
; RV32-NEXT: addi a0, a0, -256
; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; RV32-NEXT: vmv.v.x v0, a0
+; RV32-NEXT: vmv.s.x v0, a0
; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; RV32-NEXT: vrgather.vv v9, v8, v12, v0.t
; RV32-NEXT: vmsne.vi v9, v9, 0
@@ -55,7 +55,7 @@ define {<16 x i1>, <16 x i1>} @vector_deinterleave_load_v16i1_v32i1(ptr %p) {
; RV64-NEXT: lui a0, 16
; RV64-NEXT: addiw a0, a0, -256
; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; RV64-NEXT: vmv.v.x v0, a0
+; RV64-NEXT: vmv.s.x v0, a0
; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; RV64-NEXT: vrgather.vv v9, v8, v12, v0.t
; RV64-NEXT: vmsne.vi v9, v9, 0
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll
index 2eeaf0b651a258..f17920b9693374 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll
@@ -11,7 +11,7 @@ define i1 @extractelt_v1i1(ptr %x, i64 %idx) nounwind {
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vmseq.vi v0, v8, 0
-; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmv.s.x v8, zero
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vslidedown.vx v8, v8, a1
; CHECK-NEXT: vmv.x.s a0, v8
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll
index 930f571e36dee9..1864bfe11be38f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll
@@ -157,40 +157,28 @@ define <1 x half> @bitcast_i16_v1f16(i16 %a) {
; CHECK-LABEL: bitcast_i16_v1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; CHECK-NEXT: vmv.v.x v8, a0
+; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret
%b = bitcast i16 %a to <1 x half>
ret <1 x half> %b
}
define <2 x half> @bitcast_i32_v2f16(i32 %a) {
-; RV32-FP-LABEL: bitcast_i32_v2f16:
-; RV32-FP: # %bb.0:
-; RV32-FP-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; RV32-FP-NEXT: vmv.s.x v8, a0
-; RV32-FP-NEXT: ret
-;
-; RV64-FP-LABEL: bitcast_i32_v2f16:
-; RV64-FP: # %bb.0:
-; RV64-FP-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; RV64-FP-NEXT: vmv.v.x v8, a0
-; RV64-FP-NEXT: ret
+; CHECK-LABEL: bitcast_i32_v2f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
+; CHECK-NEXT: vmv.s.x v8, a0
+; CHECK-NEXT: ret
%b = bitcast i32 %a to <2 x half>
ret <2 x half> %b
}
define <1 x float> @bitcast_i32_v1f32(i32 %a) {
-; RV32-FP-LABEL: bitcast_i32_v1f32:
-; RV32-FP: # %bb.0:
-; RV32-FP-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; RV32-FP-NEXT: vmv.s.x v8, a0
-; RV32-FP-NEXT: ret
-;
-; RV64-FP-LABEL: bitcast_i32_v1f32:
-; RV64-FP: # %bb.0:
-; RV64-FP-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; RV64-FP-NEXT: vmv.v.x v8, a0
-; RV64-FP-NEXT: ret
+; CHECK-LABEL: bitcast_i32_v1f32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
+; CHECK-NEXT: vmv.s.x v8, a0
+; CHECK-NEXT: ret
%b = bitcast i32 %a to <1 x float>
ret <1 x float> %b
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll
index 25361f5463cfc6..0bd1f1491a9f48 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll
@@ -255,48 +255,56 @@ define <64 x float> @interleave_v32f32(<32 x float> %x, <32 x float> %y) {
; RV32-V128-NEXT: addi sp, sp, -16
; RV32-V128-NEXT: .cfi_def_cfa_offset 16
; RV32-V128-NEXT: csrr a0, vlenb
-; RV32-V128-NEXT: slli a0, a0, 4
+; RV32-V128-NEXT: li a1, 24
+; RV32-V128-NEXT: mul a0, a0, a1
; RV32-V128-NEXT: sub sp, sp, a0
-; RV32-V128-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
+; RV32-V128-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
+; RV32-V128-NEXT: csrr a0, vlenb
+; RV32-V128-NEXT: slli a0, a0, 3
+; RV32-V128-NEXT: add a0, sp, a0
+; RV32-V128-NEXT: addi a0, a0, 16
+; RV32-V128-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
+; RV32-V128-NEXT: addi a0, sp, 16
+; RV32-V128-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; RV32-V128-NEXT: lui a0, %hi(.LCPI10_0)
; RV32-V128-NEXT: addi a0, a0, %lo(.LCPI10_0)
; RV32-V128-NEXT: li a1, 32
-; RV32-V128-NEXT: vsetvli zero, a1, e32, m8, ta, ma
-; RV32-V128-NEXT: vle32.v v0, (a0)
-; RV32-V128-NEXT: vmv8r.v v24, v8
-; RV32-V128-NEXT: addi a0, sp, 16
-; RV32-V128-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
-; RV32-V128-NEXT: vrgather.vv v8, v24, v0
+; RV32-V128-NEXT: vsetvli zero, a1, e32, m8, ta, mu
+; RV32-V128-NEXT: vle32.v v24, (a0)
; RV32-V128-NEXT: lui a0, %hi(.LCPI10_1)
; RV32-V128-NEXT: addi a0, a0, %lo(.LCPI10_1)
-; RV32-V128-NEXT: vle32.v v24, (a0)
+; RV32-V128-NEXT: vle32.v v16, (a0)
; RV32-V128-NEXT: csrr a0, vlenb
-; RV32-V128-NEXT: slli a0, a0, 3
+; RV32-V128-NEXT: slli a0, a0, 4
; RV32-V128-NEXT: add a0, sp, a0
; RV32-V128-NEXT: addi a0, a0, 16
-; RV32-V128-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill
+; RV32-V128-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
; RV32-V128-NEXT: lui a0, 699051
; RV32-V128-NEXT: addi a0, a0, -1366
-; RV32-V128-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; RV32-V128-NEXT: vmv.v.x v0, a0
-; RV32-V128-NEXT: vsetvli zero, a1, e32, m8, ta, mu
+; RV32-V128-NEXT: vmv.s.x v0, a0
+; RV32-V128-NEXT: vrgather.vv v16, v8, v24
; RV32-V128-NEXT: csrr a0, vlenb
-; RV32-V128-NEXT: slli a0, a0, 3
+; RV32-V128-NEXT: slli a0, a0, 4
; RV32-V128-NEXT: add a0, sp, a0
; RV32-V128-NEXT: addi a0, a0, 16
; RV32-V128-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
-; RV32-V128-NEXT: vrgather.vv v8, v16, v24, v0.t
-; RV32-V128-NEXT: vmv.v.v v24, v8
+; RV32-V128-NEXT: csrr a0, vlenb
+; RV32-V128-NEXT: slli a0, a0, 3
+; RV32-V128-NEXT: add a0, sp, a0
+; RV32-V128-NEXT: addi a0, a0, 16
+; RV32-V128-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
+; RV32-V128-NEXT: vrgather.vv v16, v8, v24, v0.t
; RV32-V128-NEXT: vsetivli zero, 16, e32, m4, ta, ma
+; RV32-V128-NEXT: vmv4r.v v24, v8
; RV32-V128-NEXT: addi a0, sp, 16
; RV32-V128-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
-; RV32-V128-NEXT: vwaddu.vv v0, v8, v16
+; RV32-V128-NEXT: vwaddu.vv v0, v8, v24
; RV32-V128-NEXT: li a0, -1
-; RV32-V128-NEXT: vwmaccu.vx v0, a0, v16
+; RV32-V128-NEXT: vwmaccu.vx v0, a0, v24
; RV32-V128-NEXT: vmv8r.v v8, v0
-; RV32-V128-NEXT: vmv8r.v v16, v24
; RV32-V128-NEXT: csrr a0, vlenb
-; RV32-V128-NEXT: slli a0, a0, 4
+; RV32-V128-NEXT: li a1, 24
+; RV32-V128-NEXT: mul a0, a0, a1
; RV32-V128-NEXT: add sp, sp, a0
; RV32-V128-NEXT: addi sp, sp, 16
; RV32-V128-NEXT: ret
@@ -306,48 +314,56 @@ define <64 x float> @interleave_v32f32(<32 x float> %x, <32 x float> %y) {
; RV64-V128-NEXT: addi sp, sp, -16
; RV64-V128-NEXT: .cfi_def_cfa_offset 16
; RV64-V128-NEXT: csrr a0, vlenb
-; RV64-V128-NEXT: slli a0, a0, 4
+; RV64-V128-NEXT: li a1, 24
+; RV64-V128-NEXT: mul a0, a0, a1
; RV64-V128-NEXT: sub sp, sp, a0
-; RV64-V128-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
+; RV64-V128-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
+; RV64-V128-NEXT: csrr a0, vlenb
+; RV64-V128-NEXT: slli a0, a0, 3
+; RV64-V128-NEXT: add a0, sp, a0
+; RV64-V128-NEXT: addi a0, a0, 16
+; RV64-V128-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
+; RV64-V128-NEXT: addi a0, sp, 16
+; RV64-V128-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; RV64-V128-NEXT: lui a0, %hi(.LCPI10_0)
; RV64-V128-NEXT: addi a0, a0, %lo(.LCPI10_0)
; RV64-V128-NEXT: li a1, 32
-; RV64-V128-NEXT: vsetvli zero, a1, e32, m8, ta, ma
-; RV64-V128-NEXT: vle32.v v0, (a0)
-; RV64-V128-NEXT: vmv8r.v v24, v8
-; RV64-V128-NEXT: addi a0, sp, 16
-; RV64-V128-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
-; RV64-V128-NEXT: vrgather.vv v8, v24, v0
+; RV64-V128-NEXT: vsetvli zero, a1, e32, m8, ta, mu
+; RV64-V128-NEXT: vle32.v v24, (a0)
; RV64-V128-NEXT: lui a0, %hi(.LCPI10_1)
; RV64-V128-NEXT: addi a0, a0, %lo(.LCPI10_1)
-; RV64-V128-NEXT: vle32.v v24, (a0)
+; RV64-V128-NEXT: vle32.v v16, (a0)
; RV64-V128-NEXT: csrr a0, vlenb
-; RV64-V128-NEXT: slli a0, a0, 3
+; RV64-V128-NEXT: slli a0, a0, 4
; RV64-V128-NEXT: add a0, sp, a0
; RV64-V128-NEXT: addi a0, a0, 16
-; RV64-V128-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill
+; RV64-V128-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
; RV64-V128-NEXT: lui a0, 699051
; RV64-V128-NEXT: addiw a0, a0, -1366
-; RV64-V128-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; RV64-V128-NEXT: vmv.v.x v0, a0
-; RV64-V128-NEXT: vsetvli zero, a1, e32, m8, ta, mu
+; RV64-V128-NEXT: vmv.s.x v0, a0
+; RV64-V128-NEXT: vrgather.vv v16, v8, v24
; RV64-V128-NEXT: csrr a0, vlenb
-; RV64-V128-NEXT: slli a0, a0, 3
+; RV64-V128-NEXT: slli a0, a0, 4
; RV64-V128-NEXT: add a0, sp, a0
; RV64-V128-NEXT: addi a0, a0, 16
; RV64-V128-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
-; RV64-V128-NEXT: vrgather.vv v8, v16, v24, v0.t
-; RV64-V128-NEXT: vmv.v.v v24, v8
+; RV64-V128-NEXT: csrr a0, vlenb
+; RV64-V128-NEXT: slli a0, a0, 3
+; RV64-V128-NEXT: add a0, sp, a0
+; RV64-V128-NEXT: addi a0, a0, 16
+; RV64-V128-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
+; RV64-V128-NEXT: vrgather.vv v16, v8, v24, v0.t
; RV64-V128-NEXT: vsetivli zero, 16, e32, m4, ta, ma
+; RV64-V128-NEXT: vmv4r.v v24, v8
; RV64-V128-NEXT: addi a0, sp, 16
; RV64-V128-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
-; RV64-V128-NEXT: vwaddu.vv v0, v8, v16
+; RV64-V128-NEXT: vwaddu.vv v0, v8, v24
; RV64-V128-NEXT: li a0, -1
-; RV64-V128-NEXT: vwmaccu.vx v0, a0, v16
+; RV64-V128-NEXT: vwmaccu.vx v0, a0, v24
; RV64-V128-NEXT: vmv8r.v v8, v0
-; RV64-V128-NEXT: vmv8r.v v16, v24
; RV64-V128-NEXT: csrr a0, vlenb
-; RV64-V128-NEXT: slli a0, a0, 4
+; RV64-V128-NEXT: li a1, 24
+; RV64-V128-NEXT: mul a0, a0, a1
; RV64-V128-NEXT: add sp, sp, a0
; RV64-V128-NEXT: addi sp, sp, 16
; RV64-V128-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
index 4ba7d922249a91..e06228a79cf667 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
@@ -18,9 +18,8 @@ define <8 x float> @shuffle_v8f32(<8 x float> %x, <8 x float> %y) {
; CHECK-LABEL: shuffle_v8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: li a0, 236
-; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
-; CHECK-NEXT: vmv.v.x v0, a0
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; CHECK-NEXT: vmv.s.x v0, a0
; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
; CHECK-NEXT: ret
%s = shufflevector <8 x float> %x, <8 x float> %y, <8 x i32> <i32 8, i32 9, i32 2, i32 3, i32 12, i32 5, i32 6, i32 7>
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-i1.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-i1.ll
index 42bc54da09a0b6..113b4109b6d774 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-i1.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-i1.ll
@@ -9,7 +9,7 @@ define <1 x i1> @insertelt_v1i1(<1 x i1> %x, i1 %elt) nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
-; CHECK-NEXT: vmv.v.x v8, a0
+; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%y = insertelement <1 x i1> %x, i1 %elt, i64 0
@@ -20,7 +20,7 @@ define <1 x i1> @insertelt_idx_v1i1(<1 x i1> %x, i1 %elt, i32 zeroext %idx) noun
; CHECK-LABEL: insertelt_idx_v1i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
-; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmv.s.x v8, zero
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: addi a2, a1, 1
; CHECK-NEXT: vmv.s.x v9, a0
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
index b1da392cfadf94..f16f64630bff17 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
@@ -603,13 +603,13 @@ define void @buildvec_seq_v9i8(ptr %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 73
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; CHECK-NEXT: vmv.v.x v0, a1
+; CHECK-NEXT: vmv.s.x v0, a1
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vmv.v.i v8, 3
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: li a1, 146
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; CHECK-NEXT: vmv.v.x v0, a1
+; CHECK-NEXT: vmv.s.x v0, a1
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vmerge.vim v8, v8, 2, v0
; CHECK-NEXT: vsetivli zero, 9, e8, m1, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll
index 78b5f01ebbb53e..62684cb286cf23 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll
@@ -414,48 +414,56 @@ define <64 x i32> @interleave_v32i32(<32 x i32> %x, <32 x i32> %y) {
; RV32-V128-NEXT: addi sp, sp, -16
; RV32-V128-NEXT: .cfi_def_cfa_offset 16
; RV32-V128-NEXT: csrr a0, vlenb
-; RV32-V128-NEXT: slli a0, a0, 4
+; RV32-V128-NEXT: li a1, 24
+; RV32-V128-NEXT: mul a0, a0, a1
; RV32-V128-NEXT: sub sp, sp, a0
-; RV32-V128-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
+; RV32-V128-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
+; RV32-V128-NEXT: csrr a0, vlenb
+; RV32-V128-NEXT: slli a0, a0, 3
+; RV32-V128-NEXT: add a0, sp, a0
+; RV32-V128-NEXT: addi a0, a0, 16
+; RV32-V128-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
+; RV32-V128-NEXT: addi a0, sp, 16
+; RV32-V128-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; RV32-V128-NEXT: lui a0, %hi(.LCPI17_0)
; RV32-V128-NEXT: addi a0, a0, %lo(.LCPI17_0)
; RV32-V128-NEXT: li a1, 32
-; RV32-V128-NEXT: vsetvli zero, a1, e32, m8, ta, ma
-; RV32-V128-NEXT: vle32.v v0, (a0)
-; RV32-V128-NEXT: vmv8r.v v24, v8
-; RV32-V128-NEXT: addi a0, sp, 16
-; RV32-V128-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
-; RV32-V128-NEXT: vrgather.vv v8, v24, v0
+; RV32-V128-NEXT: vsetvli zero, a1, e32, m8, ta, mu
+; RV32-V128-NEXT: vle32.v v24, (a0)
; RV32-V128-NEXT: lui a0, %hi(.LCPI17_1)
; RV32-V128-NEXT: addi a0, a0, %lo(.LCPI17_1)
-; RV32-V128-NEXT: vle32.v v24, (a0)
+; RV32-V128-NEXT: vle32.v v16, (a0)
; RV32-V128-NEXT: csrr a0, vlenb
-; RV32-V128-NEXT: slli a0, a0, 3
+; RV32-V128-NEXT: slli a0, a0, 4
; RV32-V128-NEXT: add a0, sp, a0
; RV32-V128-NEXT: addi a0, a0, 16
-; RV32-V128-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill
+; RV32-V128-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
; RV32-V128-NEXT: lui a0, 699051
; RV32-V128-NEXT: addi a0, a0, -1366
-; RV32-V128-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; RV32-V128-NEXT: vmv.v.x v0, a0
-; RV32-V128-NEXT: vsetvli zero, a1, e32, m8, ta, mu
+; RV32-V128-NEXT: vmv.s.x v0, a0
+; RV32-V128-NEXT: vrgather.vv v16, v8, v24
; RV32-V128-NEXT: csrr a0, vlenb
-; RV32-V128-NEXT: slli a0, a0, 3
+; RV32-V128-NEXT: slli a0, a0, 4
; RV32-V128-NEXT: add a0, sp, a0
; RV32-V128-NEXT: addi a0, a0, 16
; RV32-V128-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
-; RV32-V128-NEXT: vrgather.vv v8, v16, v24, v0.t
-; RV32-V128-NEXT: vmv.v.v v24, v8
+; RV32-V128-NEXT: csrr a0, vlenb
+; RV32-V128-NEXT: slli a0, a0, 3
+; RV32-V128-NEXT: add a0, sp, a0
+; RV32-V128-NEXT: addi a0, a0, 16
+; RV32-V128-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
+; RV32-V128-NEXT: vrgather.vv v16, v8, v24, v0.t
; RV32-V128-NEXT: vsetivli zero, 16, e32, m4, ta, ma
+; RV32-V128-NEXT: vmv4r.v v24, v8
; RV32-V128-NEXT: addi a0, sp, 16
; RV32-V128-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
-; RV32-V128-NEXT: vwaddu.vv v0, v8, v16
+; RV32-V128-NEXT: vwaddu.vv v0, v8, v24
; RV32-V128-NEXT: li a0, -1
-; RV32-V128-NEXT: vwmaccu.vx v0, a0, v16
+; RV32-V128-NEXT: vwmaccu.vx v0, a0, v24
; RV32-V128-NEXT: vmv8r.v v8, v0
-; RV32-V128-NEXT: vmv8r.v v16, v24
; RV32-V128-NEXT: csrr a0, vlenb
-; RV32-V128-NEXT: slli a0, a0, 4
+; RV32-V128-NEXT: li a1, 24
+; RV32-V128-NEXT: mul a0, a0, a1
; RV32-V128-NEXT: add sp, sp, a0
; RV32-V128-NEXT: addi sp, sp, 16
; RV32-V128-NEXT: ret
@@ -465,48 +473,56 @@ define <64 x i32> @interleave_v32i32(<32 x i32> %x, <32 x i32> %y) {
; RV64-V128-NEXT: addi sp, sp, -16
; RV64-V128-NEXT: .cfi_def_cfa_offset 16
; RV64-V128-NEXT: csrr a0, vlenb
-; RV64-V128-NEXT: slli a0, a0, 4
+; RV64-V128-NEXT: li a1, 24
+; RV64-V128-NEXT: mul a0, a0, a1
; RV64-V128-NEXT: sub sp, sp, a0
-; RV64-V128-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
+; RV64-V128-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
+; RV64-V128-NEXT: csrr a0, vlenb
+; RV64-V128-NEXT: slli a0, a0, 3
+; RV64-V128-NEXT: add a0, sp, a0
+; RV64-V128-NEXT: addi a0, a0, 16
+; RV64-V128-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
+; RV64-V128-NEXT: addi a0, sp, 16
+; RV64-V128-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; RV64-V128-NEXT: lui a0, %hi(.LCPI17_0)
; RV64-V128-NEXT: addi a0, a0, %lo(.LCPI17_0)
; RV64-V128-NEXT: li a1, 32
-; RV64-V128-NEXT: vsetvli zero, a1, e32, m8, ta, ma
-; RV64-V128-NEXT: vle32.v v0, (a0)
-; RV64-V128-NEXT: vmv8r.v v24, v8
-; RV64-V128-NEXT: addi a0, sp, 16
-; RV64-V128-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
-; RV64-V128-NEXT: vrgather.vv v8, v24, v0
+; RV64-V128-NEXT: vsetvli zero, a1, e32, m8, ta, mu
+; RV64-V128-NEXT: vle32.v v24, (a0)
; RV64-V128-NEXT: lui a0, %hi(.LCPI17_1)
; RV64-V128-NEXT: addi a0, a0, %lo(.LCPI17_1)
-; RV64-V128-NEXT: vle32.v v24, (a0)
+; RV64-V128-NEXT: vle32.v v16, (a0)
; RV64-V128-NEXT: csrr a0, vlenb
-; RV64-V128-NEXT: slli a0, a0, 3
+; RV64-V128-NEXT: slli a0, a0, 4
; RV64-V128-NEXT: add a0, sp, a0
; RV64-V128-NEXT: addi a0, a0, 16
-; RV64-V128-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill
+; RV64-V128-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
; RV64-V128-NEXT: lui a0, 699051
; RV64-V128-NEXT: addiw a0, a0, -1366
-; RV64-V128-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; RV64-V128-NEXT: vmv.v.x v0, a0
-; RV64-V128-NEXT: vsetvli zero, a1, e32, m8, ta, mu
+; RV64-V128-NEXT: vmv.s.x v0, a0
+; RV64-V128-NEXT: vrgather.vv v16, v8, v24
; RV64-V128-NEXT: csrr a0, vlenb
-; RV64-V128-NEXT: slli a0, a0, 3
+; RV64-V128-NEXT: slli a0, a0, 4
; RV64-V128-NEXT: add a0, sp, a0
; RV64-V128-NEXT: addi a0, a0, 16
; RV64-V128-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
-; RV64-V128-NEXT: vrgather.vv v8, v16, v24, v0.t
-; RV64-V128-NEXT: vmv.v.v v24, v8
+; RV64-V128-NEXT: csrr a0, vlenb
+; RV64-V128-NEXT: slli a0, a0, 3
+; RV64-V128-NEXT: add a0, sp, a0
+; RV64-V128-NEXT: addi a0, a0, 16
+; RV64-V128-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
+; RV64-V128-NEXT: vrgather.vv v16, v8, v24, v0.t
; RV64-V128-NEXT: vsetivli zero, 16, e32, m4, ta, ma
+; RV64-V128-NEXT: vmv4r.v v24, v8
; RV64-V128-NEXT: addi a0, sp, 16
; RV64-V128-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
-; RV64-V128-NEXT: vwaddu.vv v0, v8, v16
+; RV64-V128-NEXT: vwaddu.vv v0, v8, v24
; RV64-V128-NEXT: li a0, -1
-; RV64-V128-NEXT: vwmaccu.vx v0, a0, v16
+; RV64-V128-NEXT: vwmaccu.vx v0, a0, v24
; RV64-V128-NEXT: vmv8r.v v8, v0
-; RV64-V128-NEXT: vmv8r.v v16, v24
; RV64-V128-NEXT: csrr a0, vlenb
-; RV64-V128-NEXT: slli a0, a0, 4
+; RV64-V128-NEXT: li a1, 24
+; RV64-V128-NEXT: mul a0, a0, a1
; RV64-V128-NEXT: add sp, sp, a0
; RV64-V128-NEXT: addi sp, sp, 16
; RV64-V128-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
index 14adf926526402..8854da087d568d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
@@ -18,9 +18,8 @@ define <8 x i32> @shuffle_v8i32(<8 x i32> %x, <8 x i32> %y) {
; CHECK-LABEL: shuffle_v8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: li a0, 203
-; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
-; CHECK-NEXT: vmv.v.x v0, a0
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; CHECK-NEXT: vmv.s.x v0, a0
; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
; CHECK-NEXT: ret
%s = shufflevector <8 x i32> %x, <8 x i32> %y, <8 x i32> <i32 0, i32 1, i32 10, i32 3, i32 12, i32 13, i32 6, i32 7>
@@ -179,36 +178,32 @@ define <8 x i64> @vrgather_shuffle_vv_v8i64(<8 x i64> %x, <8 x i64> %y) {
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV32-NEXT: vmv.v.i v16, 2
+; RV32-NEXT: li a0, 5
+; RV32-NEXT: vslide1down.vx v20, v16, a0
; RV32-NEXT: lui a0, %hi(.LCPI11_0)
; RV32-NEXT: addi a0, a0, %lo(.LCPI11_0)
-; RV32-NEXT: vle16.v v20, (a0)
-; RV32-NEXT: li a0, 5
-; RV32-NEXT: vslide1down.vx v21, v16, a0
-; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, ma
-; RV32-NEXT: vrgatherei16.vv v16, v8, v20
+; RV32-NEXT: vle16.v v21, (a0)
+; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu
; RV32-NEXT: li a0, 164
-; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
-; RV32-NEXT: vmv.v.x v0, a0
-; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV32-NEXT: vrgatherei16.vv v16, v12, v21, v0.t
+; RV32-NEXT: vmv.s.x v0, a0
+; RV32-NEXT: vrgatherei16.vv v16, v8, v21
+; RV32-NEXT: vrgatherei16.vv v16, v12, v20, v0.t
; RV32-NEXT: vmv.v.v v8, v16
; RV32-NEXT: ret
;
; RV64-LABEL: vrgather_shuffle_vv_v8i64:
; RV64: # %bb.0:
-; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
+; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: lui a0, %hi(.LCPI11_0)
; RV64-NEXT: addi a0, a0, %lo(.LCPI11_0)
; RV64-NEXT: vle64.v v20, (a0)
-; RV64-NEXT: vmv.v.i v16, 2
-; RV64-NEXT: li a0, 5
-; RV64-NEXT: vslide1down.vx v24, v16, a0
+; RV64-NEXT: vmv.v.i v24, 2
; RV64-NEXT: vrgather.vv v16, v8, v20
; RV64-NEXT: li a0, 164
-; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
-; RV64-NEXT: vmv.v.x v0, a0
-; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vrgather.vv v16, v12, v24, v0.t
+; RV64-NEXT: vmv.s.x v0, a0
+; RV64-NEXT: li a0, 5
+; RV64-NEXT: vslide1down.vx v8, v24, a0
+; RV64-NEXT: vrgather.vv v16, v12, v8, v0.t
; RV64-NEXT: vmv.v.v v8, v16
; RV64-NEXT: ret
%s = shufflevector <8 x i64> %x, <8 x i64> %y, <8 x i32> <i32 1, i32 2, i32 10, i32 5, i32 1, i32 10, i32 3, i32 13>
@@ -220,18 +215,16 @@ define <8 x i64> @vrgather_shuffle_xv_v8i64(<8 x i64> %x) {
; RV32: # %bb.0:
; RV32-NEXT: lui a0, %hi(.LCPI12_0)
; RV32-NEXT: addi a0, a0, %lo(.LCPI12_0)
-; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
+; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vle16.v v16, (a0)
; RV32-NEXT: vmv.v.i v20, -1
-; RV32-NEXT: vrgatherei16.vv v12, v20, v16
; RV32-NEXT: lui a0, %hi(.LCPI12_1)
; RV32-NEXT: addi a0, a0, %lo(.LCPI12_1)
-; RV32-NEXT: vle16.v v16, (a0)
+; RV32-NEXT: vle16.v v17, (a0)
; RV32-NEXT: li a0, 113
-; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
-; RV32-NEXT: vmv.v.x v0, a0
-; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV32-NEXT: vrgatherei16.vv v12, v8, v16, v0.t
+; RV32-NEXT: vmv.s.x v0, a0
+; RV32-NEXT: vrgatherei16.vv v12, v20, v16
+; RV32-NEXT: vrgatherei16.vv v12, v8, v17, v0.t
; RV32-NEXT: vmv.v.v v8, v12
; RV32-NEXT: ret
;
@@ -239,12 +232,10 @@ define <8 x i64> @vrgather_shuffle_xv_v8i64(<8 x i64> %x) {
; RV64: # %bb.0:
; RV64-NEXT: lui a0, %hi(.LCPI12_0)
; RV64-NEXT: addi a0, a0, %lo(.LCPI12_0)
-; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
+; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: vle64.v v16, (a0)
; RV64-NEXT: li a0, 113
-; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
-; RV64-NEXT: vmv.v.x v0, a0
-; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
+; RV64-NEXT: vmv.s.x v0, a0
; RV64-NEXT: vmv.v.i v12, -1
; RV64-NEXT: vrgather.vv v12, v8, v16, v0.t
; RV64-NEXT: vmv.v.v v8, v12
@@ -258,16 +249,14 @@ define <8 x i64> @vrgather_shuffle_vx_v8i64(<8 x i64> %x) {
; RV32: # %bb.0:
; RV32-NEXT: lui a0, %hi(.LCPI13_0)
; RV32-NEXT: addi a0, a0, %lo(.LCPI13_0)
-; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
+; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vle16.v v16, (a0)
; RV32-NEXT: vrgatherei16.vv v12, v8, v16
; RV32-NEXT: lui a0, %hi(.LCPI13_1)
; RV32-NEXT: addi a0, a0, %lo(.LCPI13_1)
; RV32-NEXT: vle16.v v8, (a0)
; RV32-NEXT: li a0, 140
-; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
-; RV32-NEXT: vmv.v.x v0, a0
-; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
+; RV32-NEXT: vmv.s.x v0, a0
; RV32-NEXT: vmv.v.i v16, 5
; RV32-NEXT: vrgatherei16.vv v12, v16, v8, v0.t
; RV32-NEXT: vmv.v.v v8, v12
@@ -277,12 +266,10 @@ define <8 x i64> @vrgather_shuffle_vx_v8i64(<8 x i64> %x) {
; RV64: # %bb.0:
; RV64-NEXT: lui a0, %hi(.LCPI13_0)
; RV64-NEXT: addi a0, a0, %lo(.LCPI13_0)
-; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
+; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: vle64.v v16, (a0)
; RV64-NEXT: li a0, 115
-; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
-; RV64-NEXT: vmv.v.x v0, a0
-; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
+; RV64-NEXT: vmv.s.x v0, a0
; RV64-NEXT: vmv.v.i v12, 5
; RV64-NEXT: vrgather.vv v12, v8, v16, v0.t
; RV64-NEXT: vmv.v.v v8, v12
@@ -389,7 +376,7 @@ define <8 x i8> @splat_ve2_we0(<8 x i8> %v, <8 x i8> %w) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: li a0, 66
-; CHECK-NEXT: vmv.v.x v0, a0
+; CHECK-NEXT: vmv.s.x v0, a0
; CHECK-NEXT: vrgather.vi v10, v8, 2
; CHECK-NEXT: vrgather.vi v10, v9, 0, v0.t
; CHECK-NEXT: vmv1r.v v8, v10
@@ -408,7 +395,7 @@ define <8 x i8> @splat_ve2_we0_ins_i0ve4(<8 x i8> %v, <8 x i8> %w) {
; CHECK-NEXT: vmv.s.x v11, a0
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; CHECK-NEXT: li a0, 66
-; CHECK-NEXT: vmv.v.x v0, a0
+; CHECK-NEXT: vmv.s.x v0, a0
; CHECK-NEXT: vrgather.vv v10, v8, v11
; CHECK-NEXT: vrgather.vi v10, v9, 0, v0.t
; CHECK-NEXT: vmv1r.v v8, v10
@@ -425,7 +412,7 @@ define <8 x i8> @splat_ve2_we0_ins_i0we4(<8 x i8> %v, <8 x i8> %w) {
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vmv.v.i v8, 4
; CHECK-NEXT: li a0, 67
-; CHECK-NEXT: vmv.v.x v0, a0
+; CHECK-NEXT: vmv.s.x v0, a0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vrgather.vv v10, v9, v8, v0.t
; CHECK-NEXT: vmv1r.v v8, v10
@@ -443,7 +430,7 @@ define <8 x i8> @splat_ve2_we0_ins_i2ve4(<8 x i8> %v, <8 x i8> %w) {
; RV32-NEXT: vmv.v.x v11, a0
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV32-NEXT: li a0, 66
-; RV32-NEXT: vmv.v.x v0, a0
+; RV32-NEXT: vmv.s.x v0, a0
; RV32-NEXT: vrgather.vv v10, v8, v11
; RV32-NEXT: vrgather.vi v10, v9, 0, v0.t
; RV32-NEXT: vmv1r.v v8, v10
@@ -457,7 +444,7 @@ define <8 x i8> @splat_ve2_we0_ins_i2ve4(<8 x i8> %v, <8 x i8> %w) {
; RV64-NEXT: vmv.v.x v11, a0
; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV64-NEXT: li a0, 66
-; RV64-NEXT: vmv.v.x v0, a0
+; RV64-NEXT: vmv.s.x v0, a0
; RV64-NEXT: vrgather.vv v10, v8, v11
; RV64-NEXT: vrgather.vi v10, v9, 0, v0.t
; RV64-NEXT: vmv1r.v v8, v10
@@ -476,7 +463,7 @@ define <8 x i8> @splat_ve2_we0_ins_i2we4(<8 x i8> %v, <8 x i8> %w) {
; CHECK-NEXT: vslideup.vi v11, v10, 2
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: li a0, 70
-; CHECK-NEXT: vmv.v.x v0, a0
+; CHECK-NEXT: vmv.s.x v0, a0
; CHECK-NEXT: vrgather.vi v10, v8, 2
; CHECK-NEXT: vrgather.vv v10, v9, v11, v0.t
; CHECK-NEXT: vmv1r.v v8, v10
@@ -499,7 +486,7 @@ define <8 x i8> @splat_ve2_we0_ins_i2ve4_i5we6(<8 x i8> %v, <8 x i8> %w) {
; RV32-NEXT: vmv.v.x v12, a0
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV32-NEXT: li a0, 98
-; RV32-NEXT: vmv.v.x v0, a0
+; RV32-NEXT: vmv.s.x v0, a0
; RV32-NEXT: vrgather.vv v10, v8, v12
; RV32-NEXT: vrgather.vv v10, v9, v11, v0.t
; RV32-NEXT: vmv1r.v v8, v10
@@ -518,7 +505,7 @@ define <8 x i8> @splat_ve2_we0_ins_i2ve4_i5we6(<8 x i8> %v, <8 x i8> %w) {
; RV64-NEXT: vmv.v.x v12, a0
; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV64-NEXT: li a0, 98
-; RV64-NEXT: vmv.v.x v0, a0
+; RV64-NEXT: vmv.s.x v0, a0
; RV64-NEXT: vrgather.vv v10, v8, v12
; RV64-NEXT: vrgather.vv v10, v9, v11, v0.t
; RV64-NEXT: vmv1r.v v8, v10
@@ -668,7 +655,7 @@ define <8 x i8> @concat_4xi8_start_undef_at_start(<8 x i8> %v, <8 x i8> %w) {
; CHECK-NEXT: vid.v v11
; CHECK-NEXT: vrgather.vv v10, v8, v11
; CHECK-NEXT: li a0, 224
-; CHECK-NEXT: vmv.v.x v0, a0
+; CHECK-NEXT: vmv.s.x v0, a0
; CHECK-NEXT: vadd.vi v8, v11, -4
; CHECK-NEXT: vrgather.vv v10, v9, v8, v0.t
; CHECK-NEXT: vmv1r.v v8, v10
@@ -684,7 +671,7 @@ define <8 x i8> @merge_start_into_end_non_contiguous(<8 x i8> %v, <8 x i8> %w) {
; CHECK-NEXT: vid.v v11
; CHECK-NEXT: vrgather.vv v10, v8, v11
; CHECK-NEXT: li a0, 144
-; CHECK-NEXT: vmv.v.x v0, a0
+; CHECK-NEXT: vmv.s.x v0, a0
; CHECK-NEXT: vadd.vi v8, v11, -4
; CHECK-NEXT: vrgather.vv v10, v9, v8, v0.t
; CHECK-NEXT: vmv1r.v v8, v10
@@ -731,7 +718,7 @@ define <8 x i8> @merge_slidedown(<8 x i8> %v, <8 x i8> %w) {
; CHECK-NEXT: vid.v v11
; CHECK-NEXT: vadd.vi v12, v11, 1
; CHECK-NEXT: li a0, 195
-; CHECK-NEXT: vmv.v.x v0, a0
+; CHECK-NEXT: vmv.s.x v0, a0
; CHECK-NEXT: vrgather.vv v10, v8, v12
; CHECK-NEXT: vrgather.vv v10, v9, v11, v0.t
; CHECK-NEXT: vmv1r.v v8, v10
@@ -749,7 +736,7 @@ define <8 x i8> @merge_non_contiguous_slideup_slidedown(<8 x i8> %v, <8 x i8> %w
; CHECK-NEXT: vadd.vi v12, v11, 2
; CHECK-NEXT: vrgather.vv v10, v8, v12
; CHECK-NEXT: li a0, 234
-; CHECK-NEXT: vmv.v.x v0, a0
+; CHECK-NEXT: vmv.s.x v0, a0
; CHECK-NEXT: vadd.vi v8, v11, -1
; CHECK-NEXT: vrgather.vv v10, v9, v8, v0.t
; CHECK-NEXT: vmv1r.v v8, v10
@@ -769,7 +756,7 @@ define <8 x i8> @unmergable(<8 x i8> %v, <8 x i8> %w) {
; CHECK-NEXT: addi a0, a0, %lo(.LCPI46_0)
; CHECK-NEXT: vle8.v v12, (a0)
; CHECK-NEXT: li a0, 234
-; CHECK-NEXT: vmv.v.x v0, a0
+; CHECK-NEXT: vmv.s.x v0, a0
; CHECK-NEXT: vrgather.vv v10, v8, v11
; CHECK-NEXT: vrgather.vv v10, v9, v12, v0.t
; CHECK-NEXT: vmv1r.v v8, v10
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll
index c8c2aea4b4ebbc..a54e82c78962aa 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll
@@ -822,11 +822,9 @@ define void @vadd_vx_v16i64(ptr %a, i64 %b, ptr %c) {
; LMULMAX2-RV32-NEXT: addi a0, a0, 32
; LMULMAX2-RV32-NEXT: vle64.v v14, (a0)
; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; LMULMAX2-RV32-NEXT: vmv.v.x v16, a2
; LMULMAX2-RV32-NEXT: li a0, 85
-; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
-; LMULMAX2-RV32-NEXT: vmv.v.x v0, a0
-; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; LMULMAX2-RV32-NEXT: vmv.s.x v0, a0
+; LMULMAX2-RV32-NEXT: vmv.v.x v16, a2
; LMULMAX2-RV32-NEXT: vmerge.vxm v16, v16, a1, v0
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; LMULMAX2-RV32-NEXT: vadd.vv v14, v14, v16
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
index ea7ab339729bc9..d2fa24b62d9801 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
@@ -1108,7 +1108,7 @@ define void @mulhu_v16i8(ptr %x) {
; RV32-NEXT: lui a1, 3
; RV32-NEXT: addi a1, a1, -2044
; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; RV32-NEXT: vmv.v.x v0, a1
+; RV32-NEXT: vmv.s.x v0, a1
; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV32-NEXT: vmv.v.i v9, 0
; RV32-NEXT: li a1, -128
@@ -1116,7 +1116,7 @@ define void @mulhu_v16i8(ptr %x) {
; RV32-NEXT: lui a1, 1
; RV32-NEXT: addi a2, a1, 32
; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; RV32-NEXT: vmv.v.x v0, a2
+; RV32-NEXT: vmv.s.x v0, a2
; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV32-NEXT: lui a2, %hi(.LCPI65_0)
; RV32-NEXT: addi a2, a2, %lo(.LCPI65_0)
@@ -1129,19 +1129,19 @@ define void @mulhu_v16i8(ptr %x) {
; RV32-NEXT: vadd.vv v8, v8, v9
; RV32-NEXT: li a2, 513
; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; RV32-NEXT: vmv.v.x v0, a2
+; RV32-NEXT: vmv.s.x v0, a2
; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV32-NEXT: vmv.v.i v9, 4
; RV32-NEXT: vmerge.vim v9, v9, 1, v0
; RV32-NEXT: addi a1, a1, 78
; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; RV32-NEXT: vmv.v.x v0, a1
+; RV32-NEXT: vmv.s.x v0, a1
; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV32-NEXT: vmerge.vim v9, v9, 3, v0
; RV32-NEXT: lui a1, 8
; RV32-NEXT: addi a1, a1, 304
; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; RV32-NEXT: vmv.v.x v0, a1
+; RV32-NEXT: vmv.s.x v0, a1
; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV32-NEXT: vmerge.vim v9, v9, 2, v0
; RV32-NEXT: vsrl.vv v8, v8, v9
@@ -1155,7 +1155,7 @@ define void @mulhu_v16i8(ptr %x) {
; RV64-NEXT: lui a1, 3
; RV64-NEXT: addiw a1, a1, -2044
; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; RV64-NEXT: vmv.v.x v0, a1
+; RV64-NEXT: vmv.s.x v0, a1
; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV64-NEXT: vmv.v.i v9, 0
; RV64-NEXT: li a1, -128
@@ -1163,7 +1163,7 @@ define void @mulhu_v16i8(ptr %x) {
; RV64-NEXT: lui a1, 1
; RV64-NEXT: addiw a2, a1, 32
; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; RV64-NEXT: vmv.v.x v0, a2
+; RV64-NEXT: vmv.s.x v0, a2
; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV64-NEXT: lui a2, %hi(.LCPI65_0)
; RV64-NEXT: addi a2, a2, %lo(.LCPI65_0)
@@ -1176,19 +1176,19 @@ define void @mulhu_v16i8(ptr %x) {
; RV64-NEXT: vadd.vv v8, v8, v9
; RV64-NEXT: li a2, 513
; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; RV64-NEXT: vmv.v.x v0, a2
+; RV64-NEXT: vmv.s.x v0, a2
; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV64-NEXT: vmv.v.i v9, 4
; RV64-NEXT: vmerge.vim v9, v9, 1, v0
; RV64-NEXT: addiw a1, a1, 78
; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; RV64-NEXT: vmv.v.x v0, a1
+; RV64-NEXT: vmv.s.x v0, a1
; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV64-NEXT: vmerge.vim v9, v9, 3, v0
; RV64-NEXT: lui a1, 8
; RV64-NEXT: addiw a1, a1, 304
; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; RV64-NEXT: vmv.v.x v0, a1
+; RV64-NEXT: vmv.s.x v0, a1
; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV64-NEXT: vmerge.vim v9, v9, 2, v0
; RV64-NEXT: vsrl.vv v8, v8, v9
@@ -1224,7 +1224,7 @@ define void @mulhu_v8i16(ptr %x) {
; CHECK-NEXT: vmulhu.vv v8, v8, v10
; CHECK-NEXT: vadd.vv v8, v8, v9
; CHECK-NEXT: li a1, 33
-; CHECK-NEXT: vmv.v.x v0, a1
+; CHECK-NEXT: vmv.s.x v0, a1
; CHECK-NEXT: vmv.v.i v9, 3
; CHECK-NEXT: vmerge.vim v9, v9, 2, v0
; CHECK-NEXT: vsetivli zero, 7, e16, m1, tu, ma
@@ -1355,7 +1355,7 @@ define void @mulhs_v16i8(ptr %x) {
; RV32-NEXT: lui a1, 5
; RV32-NEXT: addi a1, a1, -1452
; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; RV32-NEXT: vmv.v.x v0, a1
+; RV32-NEXT: vmv.s.x v0, a1
; RV32-NEXT: li a1, 57
; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV32-NEXT: vmerge.vxm v9, v9, a1, v0
@@ -1375,7 +1375,7 @@ define void @mulhs_v16i8(ptr %x) {
; RV64-NEXT: lui a1, 5
; RV64-NEXT: addiw a1, a1, -1452
; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; RV64-NEXT: vmv.v.x v0, a1
+; RV64-NEXT: vmv.s.x v0, a1
; RV64-NEXT: li a1, 57
; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV64-NEXT: vmerge.vxm v9, v9, a1, v0
@@ -1400,7 +1400,7 @@ define void @mulhs_v8i16(ptr %x) {
; RV32-NEXT: addi a1, a1, -1755
; RV32-NEXT: vmv.v.x v9, a1
; RV32-NEXT: li a1, 105
-; RV32-NEXT: vmv.v.x v0, a1
+; RV32-NEXT: vmv.s.x v0, a1
; RV32-NEXT: lui a1, 1048571
; RV32-NEXT: addi a1, a1, 1755
; RV32-NEXT: vmerge.vxm v9, v9, a1, v0
@@ -1419,7 +1419,7 @@ define void @mulhs_v8i16(ptr %x) {
; RV64-NEXT: addiw a1, a1, -1755
; RV64-NEXT: vmv.v.x v9, a1
; RV64-NEXT: li a1, 105
-; RV64-NEXT: vmv.v.x v0, a1
+; RV64-NEXT: vmv.s.x v0, a1
; RV64-NEXT: lui a1, 1048571
; RV64-NEXT: addiw a1, a1, 1755
; RV64-NEXT: vmerge.vxm v9, v9, a1, v0
@@ -4958,14 +4958,14 @@ define void @mulhu_v32i8(ptr %x) {
; LMULMAX2-RV32-NEXT: lui a2, 163907
; LMULMAX2-RV32-NEXT: addi a2, a2, -2044
; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; LMULMAX2-RV32-NEXT: vmv.v.x v0, a2
+; LMULMAX2-RV32-NEXT: vmv.s.x v0, a2
; LMULMAX2-RV32-NEXT: li a2, -128
; LMULMAX2-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; LMULMAX2-RV32-NEXT: vmerge.vxm v12, v10, a2, v0
; LMULMAX2-RV32-NEXT: lui a2, 66049
; LMULMAX2-RV32-NEXT: addi a2, a2, 32
; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; LMULMAX2-RV32-NEXT: vmv.v.x v0, a2
+; LMULMAX2-RV32-NEXT: vmv.s.x v0, a2
; LMULMAX2-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; LMULMAX2-RV32-NEXT: lui a2, %hi(.LCPI181_0)
; LMULMAX2-RV32-NEXT: addi a2, a2, %lo(.LCPI181_0)
@@ -4980,19 +4980,19 @@ define void @mulhu_v32i8(ptr %x) {
; LMULMAX2-RV32-NEXT: lui a2, 8208
; LMULMAX2-RV32-NEXT: addi a2, a2, 513
; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; LMULMAX2-RV32-NEXT: vmv.v.x v0, a2
+; LMULMAX2-RV32-NEXT: vmv.s.x v0, a2
; LMULMAX2-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; LMULMAX2-RV32-NEXT: vmerge.vim v10, v10, 1, v0
; LMULMAX2-RV32-NEXT: lui a2, 66785
; LMULMAX2-RV32-NEXT: addi a2, a2, 78
; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; LMULMAX2-RV32-NEXT: vmv.v.x v0, a2
+; LMULMAX2-RV32-NEXT: vmv.s.x v0, a2
; LMULMAX2-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; LMULMAX2-RV32-NEXT: vmerge.vim v10, v10, 3, v0
; LMULMAX2-RV32-NEXT: lui a2, 529160
; LMULMAX2-RV32-NEXT: addi a2, a2, 304
; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; LMULMAX2-RV32-NEXT: vmv.v.x v0, a2
+; LMULMAX2-RV32-NEXT: vmv.s.x v0, a2
; LMULMAX2-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; LMULMAX2-RV32-NEXT: vmerge.vim v10, v10, 2, v0
; LMULMAX2-RV32-NEXT: vsrl.vv v8, v8, v10
@@ -5008,14 +5008,14 @@ define void @mulhu_v32i8(ptr %x) {
; LMULMAX2-RV64-NEXT: lui a2, 163907
; LMULMAX2-RV64-NEXT: addiw a2, a2, -2044
; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; LMULMAX2-RV64-NEXT: vmv.v.x v0, a2
+; LMULMAX2-RV64-NEXT: vmv.s.x v0, a2
; LMULMAX2-RV64-NEXT: li a2, -128
; LMULMAX2-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; LMULMAX2-RV64-NEXT: vmerge.vxm v12, v10, a2, v0
; LMULMAX2-RV64-NEXT: lui a2, 66049
; LMULMAX2-RV64-NEXT: addiw a2, a2, 32
; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; LMULMAX2-RV64-NEXT: vmv.v.x v0, a2
+; LMULMAX2-RV64-NEXT: vmv.s.x v0, a2
; LMULMAX2-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; LMULMAX2-RV64-NEXT: lui a2, %hi(.LCPI181_0)
; LMULMAX2-RV64-NEXT: addi a2, a2, %lo(.LCPI181_0)
@@ -5030,19 +5030,19 @@ define void @mulhu_v32i8(ptr %x) {
; LMULMAX2-RV64-NEXT: lui a2, 8208
; LMULMAX2-RV64-NEXT: addiw a2, a2, 513
; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; LMULMAX2-RV64-NEXT: vmv.v.x v0, a2
+; LMULMAX2-RV64-NEXT: vmv.s.x v0, a2
; LMULMAX2-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; LMULMAX2-RV64-NEXT: vmerge.vim v10, v10, 1, v0
; LMULMAX2-RV64-NEXT: lui a2, 66785
; LMULMAX2-RV64-NEXT: addiw a2, a2, 78
; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; LMULMAX2-RV64-NEXT: vmv.v.x v0, a2
+; LMULMAX2-RV64-NEXT: vmv.s.x v0, a2
; LMULMAX2-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; LMULMAX2-RV64-NEXT: vmerge.vim v10, v10, 3, v0
; LMULMAX2-RV64-NEXT: lui a2, 529160
; LMULMAX2-RV64-NEXT: addiw a2, a2, 304
; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; LMULMAX2-RV64-NEXT: vmv.v.x v0, a2
+; LMULMAX2-RV64-NEXT: vmv.s.x v0, a2
; LMULMAX2-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; LMULMAX2-RV64-NEXT: vmerge.vim v10, v10, 2, v0
; LMULMAX2-RV64-NEXT: vsrl.vv v8, v8, v10
@@ -5075,32 +5075,26 @@ define void @mulhu_v16i16(ptr %x) {
; LMULMAX2-RV32-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; LMULMAX2-RV32-NEXT: vle16.v v10, (a0)
; LMULMAX2-RV32-NEXT: li a1, 257
-; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; LMULMAX2-RV32-NEXT: vmv.v.x v0, a1
-; LMULMAX2-RV32-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; LMULMAX2-RV32-NEXT: vmv.s.x v0, a1
; LMULMAX2-RV32-NEXT: vmv.v.i v12, 0
-; LMULMAX2-RV32-NEXT: lui a1, 1048568
-; LMULMAX2-RV32-NEXT: vmerge.vxm v14, v12, a1, v0
; LMULMAX2-RV32-NEXT: lui a1, 4
; LMULMAX2-RV32-NEXT: addi a1, a1, 64
-; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; LMULMAX2-RV32-NEXT: vmv.v.x v8, a1
-; LMULMAX2-RV32-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; LMULMAX2-RV32-NEXT: vmv.s.x v8, a1
; LMULMAX2-RV32-NEXT: lui a1, %hi(.LCPI182_0)
; LMULMAX2-RV32-NEXT: addi a1, a1, %lo(.LCPI182_0)
-; LMULMAX2-RV32-NEXT: vle16.v v16, (a1)
+; LMULMAX2-RV32-NEXT: vle16.v v14, (a1)
+; LMULMAX2-RV32-NEXT: lui a1, 1048568
+; LMULMAX2-RV32-NEXT: vmerge.vxm v16, v12, a1, v0
; LMULMAX2-RV32-NEXT: vmv1r.v v0, v8
; LMULMAX2-RV32-NEXT: vmerge.vim v12, v12, 1, v0
; LMULMAX2-RV32-NEXT: vsrl.vv v12, v10, v12
-; LMULMAX2-RV32-NEXT: vmulhu.vv v12, v12, v16
+; LMULMAX2-RV32-NEXT: vmulhu.vv v12, v12, v14
; LMULMAX2-RV32-NEXT: vsub.vv v10, v10, v12
-; LMULMAX2-RV32-NEXT: vmulhu.vv v10, v10, v14
+; LMULMAX2-RV32-NEXT: vmulhu.vv v10, v10, v16
; LMULMAX2-RV32-NEXT: vadd.vv v10, v10, v12
; LMULMAX2-RV32-NEXT: lui a1, 2
; LMULMAX2-RV32-NEXT: addi a1, a1, 289
-; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; LMULMAX2-RV32-NEXT: vmv.v.x v0, a1
-; LMULMAX2-RV32-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; LMULMAX2-RV32-NEXT: vmv.s.x v0, a1
; LMULMAX2-RV32-NEXT: vmv.v.i v12, 3
; LMULMAX2-RV32-NEXT: vmerge.vim v12, v12, 2, v0
; LMULMAX2-RV32-NEXT: vmv1r.v v0, v8
@@ -5114,32 +5108,26 @@ define void @mulhu_v16i16(ptr %x) {
; LMULMAX2-RV64-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; LMULMAX2-RV64-NEXT: vle16.v v10, (a0)
; LMULMAX2-RV64-NEXT: li a1, 257
-; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; LMULMAX2-RV64-NEXT: vmv.v.x v0, a1
-; LMULMAX2-RV64-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; LMULMAX2-RV64-NEXT: vmv.s.x v0, a1
; LMULMAX2-RV64-NEXT: vmv.v.i v12, 0
-; LMULMAX2-RV64-NEXT: lui a1, 1048568
-; LMULMAX2-RV64-NEXT: vmerge.vxm v14, v12, a1, v0
; LMULMAX2-RV64-NEXT: lui a1, 4
; LMULMAX2-RV64-NEXT: addiw a1, a1, 64
-; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; LMULMAX2-RV64-NEXT: vmv.v.x v8, a1
-; LMULMAX2-RV64-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; LMULMAX2-RV64-NEXT: vmv.s.x v8, a1
; LMULMAX2-RV64-NEXT: lui a1, %hi(.LCPI182_0)
; LMULMAX2-RV64-NEXT: addi a1, a1, %lo(.LCPI182_0)
-; LMULMAX2-RV64-NEXT: vle16.v v16, (a1)
+; LMULMAX2-RV64-NEXT: vle16.v v14, (a1)
+; LMULMAX2-RV64-NEXT: lui a1, 1048568
+; LMULMAX2-RV64-NEXT: vmerge.vxm v16, v12, a1, v0
; LMULMAX2-RV64-NEXT: vmv1r.v v0, v8
; LMULMAX2-RV64-NEXT: vmerge.vim v12, v12, 1, v0
; LMULMAX2-RV64-NEXT: vsrl.vv v12, v10, v12
-; LMULMAX2-RV64-NEXT: vmulhu.vv v12, v12, v16
+; LMULMAX2-RV64-NEXT: vmulhu.vv v12, v12, v14
; LMULMAX2-RV64-NEXT: vsub.vv v10, v10, v12
-; LMULMAX2-RV64-NEXT: vmulhu.vv v10, v10, v14
+; LMULMAX2-RV64-NEXT: vmulhu.vv v10, v10, v16
; LMULMAX2-RV64-NEXT: vadd.vv v10, v10, v12
; LMULMAX2-RV64-NEXT: lui a1, 2
; LMULMAX2-RV64-NEXT: addiw a1, a1, 289
-; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; LMULMAX2-RV64-NEXT: vmv.v.x v0, a1
-; LMULMAX2-RV64-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; LMULMAX2-RV64-NEXT: vmv.s.x v0, a1
; LMULMAX2-RV64-NEXT: vmv.v.i v12, 3
; LMULMAX2-RV64-NEXT: vmerge.vim v12, v12, 2, v0
; LMULMAX2-RV64-NEXT: vmv1r.v v0, v8
@@ -5174,9 +5162,7 @@ define void @mulhu_v8i32(ptr %x) {
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; LMULMAX2-NEXT: vle32.v v8, (a0)
; LMULMAX2-NEXT: li a1, 68
-; LMULMAX2-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
-; LMULMAX2-NEXT: vmv.v.x v0, a1
-; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; LMULMAX2-NEXT: vmv.s.x v0, a1
; LMULMAX2-NEXT: lui a1, %hi(.LCPI183_0)
; LMULMAX2-NEXT: addi a1, a1, %lo(.LCPI183_0)
; LMULMAX2-NEXT: vle32.v v10, (a1)
@@ -5188,9 +5174,7 @@ define void @mulhu_v8i32(ptr %x) {
; LMULMAX2-NEXT: vmulhu.vv v8, v8, v12
; LMULMAX2-NEXT: vadd.vv v8, v8, v10
; LMULMAX2-NEXT: li a1, 136
-; LMULMAX2-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
-; LMULMAX2-NEXT: vmv.v.x v0, a1
-; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; LMULMAX2-NEXT: vmv.s.x v0, a1
; LMULMAX2-NEXT: vmv.v.i v10, 2
; LMULMAX2-NEXT: vmerge.vim v10, v10, 1, v0
; LMULMAX2-NEXT: vsrl.vv v8, v8, v10
@@ -5387,7 +5371,7 @@ define void @mulhs_v32i8(ptr %x) {
; LMULMAX2-RV32-NEXT: lui a2, 304453
; LMULMAX2-RV32-NEXT: addi a2, a2, -1452
; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; LMULMAX2-RV32-NEXT: vmv.v.x v0, a2
+; LMULMAX2-RV32-NEXT: vmv.s.x v0, a2
; LMULMAX2-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; LMULMAX2-RV32-NEXT: vmerge.vim v10, v10, 1, v0
; LMULMAX2-RV32-NEXT: li a1, -123
@@ -5408,7 +5392,7 @@ define void @mulhs_v32i8(ptr %x) {
; LMULMAX2-RV64-NEXT: lui a2, 304453
; LMULMAX2-RV64-NEXT: addiw a2, a2, -1452
; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; LMULMAX2-RV64-NEXT: vmv.v.x v0, a2
+; LMULMAX2-RV64-NEXT: vmv.s.x v0, a2
; LMULMAX2-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; LMULMAX2-RV64-NEXT: vmerge.vim v10, v10, 1, v0
; LMULMAX2-RV64-NEXT: li a1, -123
@@ -5429,7 +5413,7 @@ define void @mulhs_v32i8(ptr %x) {
; LMULMAX1-RV32-NEXT: lui a2, 5
; LMULMAX1-RV32-NEXT: addi a2, a2, -1452
; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; LMULMAX1-RV32-NEXT: vmv.v.x v0, a2
+; LMULMAX1-RV32-NEXT: vmv.s.x v0, a2
; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; LMULMAX1-RV32-NEXT: vmv.v.i v10, -9
; LMULMAX1-RV32-NEXT: vmerge.vim v10, v10, 9, v0
@@ -5448,7 +5432,7 @@ define void @mulhs_v32i8(ptr %x) {
; LMULMAX1-RV64-NEXT: lui a2, 5
; LMULMAX1-RV64-NEXT: addiw a2, a2, -1452
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; LMULMAX1-RV64-NEXT: vmv.v.x v0, a2
+; LMULMAX1-RV64-NEXT: vmv.s.x v0, a2
; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; LMULMAX1-RV64-NEXT: vmv.v.i v10, -9
; LMULMAX1-RV64-NEXT: vmerge.vim v10, v10, 9, v0
@@ -5473,11 +5457,9 @@ define void @mulhs_v16i16(ptr %x) {
; LMULMAX2-RV32-NEXT: vmv.v.x v10, a1
; LMULMAX2-RV32-NEXT: lui a1, 7
; LMULMAX2-RV32-NEXT: addi a1, a1, -1687
-; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; LMULMAX2-RV32-NEXT: vmv.v.x v0, a1
+; LMULMAX2-RV32-NEXT: vmv.s.x v0, a1
; LMULMAX2-RV32-NEXT: lui a1, 1048571
; LMULMAX2-RV32-NEXT: addi a1, a1, 1755
-; LMULMAX2-RV32-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; LMULMAX2-RV32-NEXT: vmerge.vxm v10, v10, a1, v0
; LMULMAX2-RV32-NEXT: vmulh.vv v8, v8, v10
; LMULMAX2-RV32-NEXT: vsra.vi v8, v8, 1
@@ -5495,11 +5477,9 @@ define void @mulhs_v16i16(ptr %x) {
; LMULMAX2-RV64-NEXT: vmv.v.x v10, a1
; LMULMAX2-RV64-NEXT: lui a1, 7
; LMULMAX2-RV64-NEXT: addiw a1, a1, -1687
-; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; LMULMAX2-RV64-NEXT: vmv.v.x v0, a1
+; LMULMAX2-RV64-NEXT: vmv.s.x v0, a1
; LMULMAX2-RV64-NEXT: lui a1, 1048571
; LMULMAX2-RV64-NEXT: addiw a1, a1, 1755
-; LMULMAX2-RV64-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; LMULMAX2-RV64-NEXT: vmerge.vxm v10, v10, a1, v0
; LMULMAX2-RV64-NEXT: vmulh.vv v8, v8, v10
; LMULMAX2-RV64-NEXT: vsra.vi v8, v8, 1
@@ -5515,7 +5495,7 @@ define void @mulhs_v16i16(ptr %x) {
; LMULMAX1-NEXT: addi a1, a0, 16
; LMULMAX1-NEXT: vle16.v v9, (a1)
; LMULMAX1-NEXT: li a2, 105
-; LMULMAX1-NEXT: vmv.v.x v0, a2
+; LMULMAX1-NEXT: vmv.s.x v0, a2
; LMULMAX1-NEXT: vmv.v.i v10, 7
; LMULMAX1-NEXT: vmerge.vim v10, v10, -7, v0
; LMULMAX1-NEXT: vdiv.vv v9, v9, v10
@@ -5538,11 +5518,9 @@ define void @mulhs_v8i32(ptr %x) {
; LMULMAX2-RV32-NEXT: addi a1, a1, 1639
; LMULMAX2-RV32-NEXT: vmv.v.x v10, a1
; LMULMAX2-RV32-NEXT: li a1, 85
-; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
-; LMULMAX2-RV32-NEXT: vmv.v.x v0, a1
+; LMULMAX2-RV32-NEXT: vmv.s.x v0, a1
; LMULMAX2-RV32-NEXT: lui a1, 629146
; LMULMAX2-RV32-NEXT: addi a1, a1, -1639
-; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; LMULMAX2-RV32-NEXT: vmerge.vxm v10, v10, a1, v0
; LMULMAX2-RV32-NEXT: vmulh.vv v8, v8, v10
; LMULMAX2-RV32-NEXT: vsrl.vi v10, v8, 31
@@ -5625,16 +5603,13 @@ define void @mulhs_v4i64(ptr %x) {
; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; LMULMAX2-RV32-NEXT: vmv.v.x v10, a2
; LMULMAX2-RV32-NEXT: li a2, 17
-; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
-; LMULMAX2-RV32-NEXT: vmv.v.x v0, a2
+; LMULMAX2-RV32-NEXT: vmv.s.x v0, a2
; LMULMAX2-RV32-NEXT: addi a1, a1, 1366
-; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; LMULMAX2-RV32-NEXT: vmerge.vxm v10, v10, a1, v0
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; LMULMAX2-RV32-NEXT: vmulh.vv v10, v8, v10
; LMULMAX2-RV32-NEXT: li a1, 51
-; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
-; LMULMAX2-RV32-NEXT: vmv.v.x v0, a1
+; LMULMAX2-RV32-NEXT: vmv.s.x v0, a1
; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; LMULMAX2-RV32-NEXT: vmv.v.i v12, -1
; LMULMAX2-RV32-NEXT: vmerge.vim v12, v12, 0, v0
@@ -5643,8 +5618,7 @@ define void @mulhs_v4i64(ptr %x) {
; LMULMAX2-RV32-NEXT: li a1, 63
; LMULMAX2-RV32-NEXT: vsrl.vx v8, v12, a1
; LMULMAX2-RV32-NEXT: li a1, 68
-; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
-; LMULMAX2-RV32-NEXT: vmv.v.x v0, a1
+; LMULMAX2-RV32-NEXT: vmv.s.x v0, a1
; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; LMULMAX2-RV32-NEXT: vmv.v.i v10, 0
; LMULMAX2-RV32-NEXT: vmerge.vim v10, v10, 1, v0
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access-zve32x.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access-zve32x.ll
index f382394ea022ed..8acc70faaa1fc9 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access-zve32x.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access-zve32x.ll
@@ -21,7 +21,7 @@ define <4 x i1> @load_large_vector(ptr %p) {
; ZVE32X-NEXT: vmv.s.x v8, a4
; ZVE32X-NEXT: vand.vi v8, v8, 1
; ZVE32X-NEXT: vmsne.vi v0, v8, 0
-; ZVE32X-NEXT: vmv.v.i v8, 0
+; ZVE32X-NEXT: vmv.s.x v8, zero
; ZVE32X-NEXT: vmerge.vim v9, v8, 1, v0
; ZVE32X-NEXT: xor a0, a0, a7
; ZVE32X-NEXT: snez a0, a0
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
index 4cce6be15d5d89..c51c0c2bf7e6fe 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
@@ -131,16 +131,16 @@ define {<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>} @load_
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 78
+; RV32-NEXT: li a3, 82
; RV32-NEXT: mul a2, a2, a3
; RV32-NEXT: sub sp, sp, a2
-; RV32-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0xce, 0x00, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 78 * vlenb
+; RV32-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0xd2, 0x00, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 82 * vlenb
; RV32-NEXT: addi a3, a1, 256
; RV32-NEXT: li a2, 32
; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; RV32-NEXT: vle32.v v16, (a3)
; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: li a4, 53
+; RV32-NEXT: li a4, 57
; RV32-NEXT: mul a3, a3, a4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
@@ -155,122 +155,150 @@ define {<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>} @load_
; RV32-NEXT: vs4r.v v24, (a3) # Unknown-size Folded Spill
; RV32-NEXT: vadd.vi v8, v24, -4
; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: li a4, 13
-; RV32-NEXT: mul a3, a3, a4
+; RV32-NEXT: slli a4, a3, 4
+; RV32-NEXT: add a3, a4, a3
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vs4r.v v8, (a3) # Unknown-size Folded Spill
-; RV32-NEXT: vrgather.vv v4, v16, v8
+; RV32-NEXT: vrgather.vv v12, v16, v8
; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: li a4, 41
+; RV32-NEXT: li a4, 45
; RV32-NEXT: mul a3, a3, a4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs4r.v v4, (a3) # Unknown-size Folded Spill
+; RV32-NEXT: vs4r.v v12, (a3) # Unknown-size Folded Spill
; RV32-NEXT: vadd.vi v8, v24, -10
; RV32-NEXT: lui a3, 12
-; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; RV32-NEXT: vmv.v.x v0, a3
+; RV32-NEXT: vmv.s.x v0, a3
; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: li a4, 29
-; RV32-NEXT: mul a3, a3, a4
+; RV32-NEXT: slli a4, a3, 5
+; RV32-NEXT: add a3, a4, a3
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vs1r.v v0, (a3) # Unknown-size Folded Spill
; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; RV32-NEXT: vslidedown.vi v16, v16, 16
; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: li a4, 69
-; RV32-NEXT: mul a3, a3, a4
+; RV32-NEXT: slli a4, a3, 6
+; RV32-NEXT: add a3, a4, a3
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, mu
-; RV32-NEXT: vrgather.vv v4, v16, v8, v0.t
-; RV32-NEXT: lui a3, %hi(.LCPI6_0)
-; RV32-NEXT: addi a3, a3, %lo(.LCPI6_0)
-; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
-; RV32-NEXT: vle32.v v24, (a3)
-; RV32-NEXT: vle32.v v16, (a1)
+; RV32-NEXT: vrgather.vv v12, v16, v8, v0.t
; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: li a4, 61
+; RV32-NEXT: li a4, 41
; RV32-NEXT: mul a3, a3, a4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill
-; RV32-NEXT: addi a1, a1, 128
-; RV32-NEXT: vrgather.vv v8, v16, v24
-; RV32-NEXT: lui a3, %hi(.LCPI6_1)
-; RV32-NEXT: addi a3, a3, %lo(.LCPI6_1)
-; RV32-NEXT: lui a4, 1
-; RV32-NEXT: addi a4, a4, -64
-; RV32-NEXT: vle32.v v16, (a3)
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: li a5, 21
-; RV32-NEXT: mul a3, a3, a5
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill
+; RV32-NEXT: vs4r.v v12, (a3) # Unknown-size Folded Spill
+; RV32-NEXT: addi a3, a1, 128
+; RV32-NEXT: lui a4, %hi(.LCPI6_0)
+; RV32-NEXT: addi a4, a4, %lo(.LCPI6_0)
+; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, mu
+; RV32-NEXT: lui a5, %hi(.LCPI6_1)
+; RV32-NEXT: addi a5, a5, %lo(.LCPI6_1)
+; RV32-NEXT: lui a6, 1
+; RV32-NEXT: vle32.v v8, (a4)
+; RV32-NEXT: csrr a4, vlenb
+; RV32-NEXT: slli a7, a4, 3
+; RV32-NEXT: add a4, a7, a4
+; RV32-NEXT: add a4, sp, a4
+; RV32-NEXT: addi a4, a4, 16
+; RV32-NEXT: vs8r.v v8, (a4) # Unknown-size Folded Spill
; RV32-NEXT: vle32.v v16, (a1)
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a3, 45
-; RV32-NEXT: mul a1, a1, a3
+; RV32-NEXT: li a4, 73
+; RV32-NEXT: mul a1, a1, a4
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill
-; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; RV32-NEXT: vmv.v.x v0, a4
+; RV32-NEXT: vle32.v v8, (a5)
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a3, a1, 4
+; RV32-NEXT: li a4, 25
+; RV32-NEXT: mul a1, a1, a4
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
+; RV32-NEXT: vle32.v v8, (a3)
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li a3, 49
+; RV32-NEXT: mul a1, a1, a3
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
+; RV32-NEXT: addi a1, a6, -64
+; RV32-NEXT: vmv.s.x v24, a1
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 3
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vs1r.v v24, (a1) # Unknown-size Folded Spill
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a3, a1, 3
; RV32-NEXT: add a1, a3, a1
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vs1r.v v0, (a1) # Unknown-size Folded Spill
-; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, mu
+; RV32-NEXT: vl8r.v v0, (a1) # Unknown-size Folded Reload
+; RV32-NEXT: vrgather.vv v24, v16, v0
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a3, 21
+; RV32-NEXT: slli a1, a1, 3
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl1r.v v2, (a1) # Unknown-size Folded Reload
+; RV32-NEXT: vmv1r.v v0, v2
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li a3, 25
; RV32-NEXT: mul a1, a1, a3
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
-; RV32-NEXT: vrgather.vv v8, v16, v24, v0.t
+; RV32-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload
+; RV32-NEXT: vrgather.vv v24, v8, v16, v0.t
; RV32-NEXT: vsetivli zero, 12, e32, m4, tu, ma
-; RV32-NEXT: vmv.v.v v4, v8
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a3, 21
+; RV32-NEXT: li a3, 41
; RV32-NEXT: mul a1, a1, a3
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vs4r.v v4, (a1) # Unknown-size Folded Spill
+; RV32-NEXT: vl4r.v v8, (a1) # Unknown-size Folded Reload
+; RV32-NEXT: vmv.v.v v8, v24
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li a3, 41
+; RV32-NEXT: mul a1, a1, a3
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vs4r.v v8, (a1) # Unknown-size Folded Spill
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: li a3, 37
; RV32-NEXT: mul a1, a1, a3
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl4r.v v24, (a1) # Unknown-size Folded Reload
-; RV32-NEXT: vadd.vi v8, v24, -2
+; RV32-NEXT: vl4r.v v12, (a1) # Unknown-size Folded Reload
+; RV32-NEXT: vadd.vi v16, v12, -2
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a3, 53
+; RV32-NEXT: li a3, 57
; RV32-NEXT: mul a1, a1, a3
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload
-; RV32-NEXT: vrgather.vv v4, v16, v8
-; RV32-NEXT: vadd.vi v8, v24, -8
+; RV32-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
+; RV32-NEXT: vrgather.vv v8, v24, v16
+; RV32-NEXT: vadd.vi v16, v12, -8
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a3, 29
-; RV32-NEXT: mul a1, a1, a3
+; RV32-NEXT: slli a3, a1, 5
+; RV32-NEXT: add a1, a3, a1
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload
+; RV32-NEXT: vmv1r.v v1, v0
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a3, 69
-; RV32-NEXT: mul a1, a1, a3
+; RV32-NEXT: slli a3, a1, 6
+; RV32-NEXT: add a1, a3, a1
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload
-; RV32-NEXT: vrgather.vv v4, v16, v8, v0.t
+; RV32-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
+; RV32-NEXT: vrgather.vv v8, v24, v16, v0.t
+; RV32-NEXT: vmv.v.v v4, v8
; RV32-NEXT: lui a1, %hi(.LCPI6_2)
; RV32-NEXT: addi a1, a1, %lo(.LCPI6_2)
; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, mu
@@ -279,42 +307,37 @@ define {<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>} @load_
; RV32-NEXT: vle32.v v16, (a1)
; RV32-NEXT: vle32.v v8, (a3)
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a3, a1, 2
-; RV32-NEXT: add a1, a3, a1
+; RV32-NEXT: li a3, 25
+; RV32-NEXT: mul a1, a1, a3
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a3, 61
+; RV32-NEXT: li a3, 73
; RV32-NEXT: mul a1, a1, a3
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
-; RV32-NEXT: vrgather.vv v8, v24, v16
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a3, a1, 4
-; RV32-NEXT: add a1, a3, a1
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload
+; RV32-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
+; RV32-NEXT: vrgather.vv v24, v8, v16
+; RV32-NEXT: vmv1r.v v0, v2
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a3, 45
+; RV32-NEXT: li a3, 49
; RV32-NEXT: mul a1, a1, a3
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
+; RV32-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a3, a1, 2
-; RV32-NEXT: add a1, a3, a1
+; RV32-NEXT: li a3, 25
+; RV32-NEXT: mul a1, a1, a3
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload
-; RV32-NEXT: vrgather.vv v8, v24, v16, v0.t
+; RV32-NEXT: vrgather.vv v24, v8, v16, v0.t
; RV32-NEXT: vsetivli zero, 12, e32, m4, tu, ma
-; RV32-NEXT: vmv.v.v v4, v8
+; RV32-NEXT: vmv.v.v v4, v24
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a3, a1, 4
-; RV32-NEXT: add a1, a3, a1
+; RV32-NEXT: li a3, 25
+; RV32-NEXT: mul a1, a1, a3
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vs4r.v v4, (a1) # Unknown-size Folded Spill
@@ -323,12 +346,12 @@ define {<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>} @load_
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; RV32-NEXT: vle32.v v8, (a1)
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a3, 53
+; RV32-NEXT: li a3, 57
; RV32-NEXT: mul a1, a1, a3
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl8r.v v0, (a1) # Unknown-size Folded Reload
-; RV32-NEXT: vrgather.vv v12, v0, v8
+; RV32-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload
+; RV32-NEXT: vrgather.vv v12, v16, v8
; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: li a3, 37
; RV32-NEXT: mul a1, a1, a3
@@ -337,87 +360,104 @@ define {<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>} @load_
; RV32-NEXT: vl4r.v v8, (a1) # Unknown-size Folded Reload
; RV32-NEXT: vadd.vi v8, v8, -6
; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a3, a1, 3
+; RV32-NEXT: add a1, a3, a1
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vs4r.v v8, (a1) # Unknown-size Folded Spill
+; RV32-NEXT: vmv1r.v v0, v1
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a3, 29
-; RV32-NEXT: mul a1, a1, a3
+; RV32-NEXT: slli a3, a1, 6
+; RV32-NEXT: add a1, a3, a1
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl1r.v v1, (a1) # Unknown-size Folded Reload
-; RV32-NEXT: vmv1r.v v0, v1
+; RV32-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload
+; RV32-NEXT: vrgather.vv v12, v16, v8, v0.t
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a3, 69
+; RV32-NEXT: li a3, 37
; RV32-NEXT: mul a1, a1, a3
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload
-; RV32-NEXT: vrgather.vv v12, v16, v8, v0.t
-; RV32-NEXT: vmv.v.v v4, v12
+; RV32-NEXT: vs4r.v v12, (a1) # Unknown-size Folded Spill
; RV32-NEXT: lui a1, %hi(.LCPI6_5)
; RV32-NEXT: addi a1, a1, %lo(.LCPI6_5)
-; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
+; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, mu
+; RV32-NEXT: lui a3, %hi(.LCPI6_6)
+; RV32-NEXT: addi a3, a3, %lo(.LCPI6_6)
; RV32-NEXT: vle32.v v16, (a1)
+; RV32-NEXT: vle32.v v8, (a3)
+; RV32-NEXT: addi a1, sp, 16
+; RV32-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
+; RV32-NEXT: li a1, 960
+; RV32-NEXT: vmv.s.x v0, a1
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 3
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vs1r.v v0, (a1) # Unknown-size Folded Spill
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a3, 61
+; RV32-NEXT: li a3, 73
; RV32-NEXT: mul a1, a1, a3
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
; RV32-NEXT: vrgather.vv v8, v24, v16
-; RV32-NEXT: lui a1, %hi(.LCPI6_6)
-; RV32-NEXT: addi a1, a1, %lo(.LCPI6_6)
-; RV32-NEXT: li a3, 960
-; RV32-NEXT: vle32.v v24, (a1)
-; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; RV32-NEXT: vmv.v.x v0, a3
-; RV32-NEXT: addi a1, sp, 16
-; RV32-NEXT: vs1r.v v0, (a1) # Unknown-size Folded Spill
-; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, mu
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a3, 45
+; RV32-NEXT: li a3, 49
; RV32-NEXT: mul a1, a1, a3
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload
+; RV32-NEXT: addi a1, sp, 16
+; RV32-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
; RV32-NEXT: vrgather.vv v8, v16, v24, v0.t
; RV32-NEXT: vsetivli zero, 10, e32, m4, tu, ma
-; RV32-NEXT: vmv.v.v v4, v8
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a3, a1, 2
-; RV32-NEXT: add a1, a3, a1
+; RV32-NEXT: li a3, 37
+; RV32-NEXT: mul a1, a1, a3
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vs4r.v v4, (a1) # Unknown-size Folded Spill
+; RV32-NEXT: vl4r.v v12, (a1) # Unknown-size Folded Reload
+; RV32-NEXT: vmv.v.v v12, v8
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li a3, 37
+; RV32-NEXT: mul a1, a1, a3
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vs4r.v v12, (a1) # Unknown-size Folded Spill
; RV32-NEXT: lui a1, %hi(.LCPI6_7)
; RV32-NEXT: addi a1, a1, %lo(.LCPI6_7)
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; RV32-NEXT: vle32.v v8, (a1)
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a3, 53
+; RV32-NEXT: li a3, 57
; RV32-NEXT: mul a1, a1, a3
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
; RV32-NEXT: vrgather.vv v12, v24, v8
-; RV32-NEXT: vmv1r.v v0, v1
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a3, 13
-; RV32-NEXT: mul a1, a1, a3
+; RV32-NEXT: slli a3, a1, 5
+; RV32-NEXT: add a1, a3, a1
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a3, a1, 4
+; RV32-NEXT: add a1, a3, a1
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vl4r.v v8, (a1) # Unknown-size Folded Reload
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a3, 69
-; RV32-NEXT: mul a1, a1, a3
+; RV32-NEXT: slli a3, a1, 6
+; RV32-NEXT: add a1, a3, a1
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
; RV32-NEXT: vrgather.vv v12, v24, v8, v0.t
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a3, 37
-; RV32-NEXT: mul a1, a1, a3
+; RV32-NEXT: slli a3, a1, 5
+; RV32-NEXT: add a1, a3, a1
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vs4r.v v12, (a1) # Unknown-size Folded Spill
@@ -426,130 +466,132 @@ define {<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>} @load_
; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, mu
; RV32-NEXT: lui a3, %hi(.LCPI6_9)
; RV32-NEXT: addi a3, a3, %lo(.LCPI6_9)
-; RV32-NEXT: vle32.v v0, (a1)
+; RV32-NEXT: vle32.v v24, (a1)
; RV32-NEXT: vle32.v v8, (a3)
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a3, 29
-; RV32-NEXT: mul a1, a1, a3
+; RV32-NEXT: slli a3, a1, 4
+; RV32-NEXT: add a1, a3, a1
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a3, 61
+; RV32-NEXT: li a3, 73
; RV32-NEXT: mul a1, a1, a3
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
-; RV32-NEXT: vrgather.vv v8, v24, v0
-; RV32-NEXT: addi a1, sp, 16
+; RV32-NEXT: vl8r.v v0, (a1) # Unknown-size Folded Reload
+; RV32-NEXT: vrgather.vv v8, v0, v24
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 3
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a3, 29
-; RV32-NEXT: mul a1, a1, a3
+; RV32-NEXT: slli a3, a1, 4
+; RV32-NEXT: add a1, a3, a1
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
; RV32-NEXT: vrgather.vv v8, v16, v24, v0.t
; RV32-NEXT: vsetivli zero, 10, e32, m4, tu, ma
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a3, 37
-; RV32-NEXT: mul a1, a1, a3
+; RV32-NEXT: slli a3, a1, 5
+; RV32-NEXT: add a1, a3, a1
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vl4r.v v12, (a1) # Unknown-size Folded Reload
; RV32-NEXT: vmv.v.v v12, v8
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a3, 37
-; RV32-NEXT: mul a1, a1, a3
+; RV32-NEXT: slli a3, a1, 5
+; RV32-NEXT: add a1, a3, a1
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vs4r.v v12, (a1) # Unknown-size Folded Spill
-; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
+; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, mu
+; RV32-NEXT: lui a1, %hi(.LCPI6_10)
+; RV32-NEXT: addi a1, a1, %lo(.LCPI6_10)
+; RV32-NEXT: vle32.v v8, (a1)
+; RV32-NEXT: lui a1, 15
+; RV32-NEXT: vmv.s.x v1, a1
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a3, 53
+; RV32-NEXT: li a3, 57
; RV32-NEXT: mul a1, a1, a3
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
+; RV32-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload
; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a3, a1, 3
+; RV32-NEXT: add a1, a3, a1
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vl4r.v v12, (a1) # Unknown-size Folded Reload
-; RV32-NEXT: vrgather.vv v4, v8, v12
-; RV32-NEXT: lui a1, %hi(.LCPI6_10)
-; RV32-NEXT: addi a1, a1, %lo(.LCPI6_10)
-; RV32-NEXT: lui a3, 15
-; RV32-NEXT: vle32.v v8, (a1)
-; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; RV32-NEXT: vmv.v.x v2, a3
-; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, mu
-; RV32-NEXT: vmv1r.v v0, v2
+; RV32-NEXT: vrgather.vv v4, v16, v12
+; RV32-NEXT: vmv1r.v v0, v1
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a3, 69
-; RV32-NEXT: mul a1, a1, a3
+; RV32-NEXT: slli a3, a1, 6
+; RV32-NEXT: add a1, a3, a1
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload
; RV32-NEXT: vrgather.vv v4, v16, v8, v0.t
; RV32-NEXT: lui a1, %hi(.LCPI6_11)
; RV32-NEXT: addi a1, a1, %lo(.LCPI6_11)
-; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
-; RV32-NEXT: vle32.v v16, (a1)
+; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, mu
+; RV32-NEXT: lui a3, %hi(.LCPI6_12)
+; RV32-NEXT: addi a3, a3, %lo(.LCPI6_12)
+; RV32-NEXT: vle32.v v24, (a1)
+; RV32-NEXT: vle32.v v8, (a3)
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a3, 61
+; RV32-NEXT: li a3, 57
; RV32-NEXT: mul a1, a1, a3
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
-; RV32-NEXT: vrgather.vv v8, v24, v16
-; RV32-NEXT: lui a1, %hi(.LCPI6_12)
-; RV32-NEXT: addi a1, a1, %lo(.LCPI6_12)
-; RV32-NEXT: li a3, 1008
-; RV32-NEXT: vle32.v v16, (a1)
-; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; RV32-NEXT: vmv.v.x v0, a3
+; RV32-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
+; RV32-NEXT: li a1, 1008
+; RV32-NEXT: vmv.s.x v2, a1
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a3, 53
+; RV32-NEXT: li a3, 73
; RV32-NEXT: mul a1, a1, a3
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vs1r.v v0, (a1) # Unknown-size Folded Spill
-; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, mu
+; RV32-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload
+; RV32-NEXT: vrgather.vv v8, v16, v24
+; RV32-NEXT: vmv1r.v v0, v2
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a3, 45
+; RV32-NEXT: li a3, 49
; RV32-NEXT: mul a1, a1, a3
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
-; RV32-NEXT: vrgather.vv v8, v24, v16, v0.t
-; RV32-NEXT: vsetivli zero, 10, e32, m4, tu, ma
-; RV32-NEXT: vmv.v.v v4, v8
+; RV32-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a3, 29
+; RV32-NEXT: li a3, 57
; RV32-NEXT: mul a1, a1, a3
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vs4r.v v4, (a1) # Unknown-size Folded Spill
+; RV32-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
+; RV32-NEXT: vrgather.vv v8, v16, v24, v0.t
+; RV32-NEXT: vsetivli zero, 10, e32, m4, tu, ma
+; RV32-NEXT: vmv.v.v v4, v8
; RV32-NEXT: lui a1, %hi(.LCPI6_13)
; RV32-NEXT: addi a1, a1, %lo(.LCPI6_13)
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; RV32-NEXT: vle32.v v8, (a1)
-; RV32-NEXT: vmv1r.v v0, v2
+; RV32-NEXT: vmv1r.v v0, v1
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a3, 69
+; RV32-NEXT: li a3, 45
; RV32-NEXT: mul a1, a1, a3
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
+; RV32-NEXT: vl4r.v v12, (a1) # Unknown-size Folded Reload
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a3, 41
-; RV32-NEXT: mul a1, a1, a3
+; RV32-NEXT: slli a3, a1, 6
+; RV32-NEXT: add a1, a3, a1
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl4r.v v12, (a1) # Unknown-size Folded Reload
-; RV32-NEXT: vrgather.vv v12, v24, v8, v0.t
+; RV32-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload
+; RV32-NEXT: vrgather.vv v12, v16, v8, v0.t
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a3, 41
+; RV32-NEXT: li a3, 45
; RV32-NEXT: mul a1, a1, a3
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
@@ -559,43 +601,38 @@ define {<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>} @load_
; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, mu
; RV32-NEXT: lui a2, %hi(.LCPI6_15)
; RV32-NEXT: addi a2, a2, %lo(.LCPI6_15)
-; RV32-NEXT: vle32.v v24, (a1)
+; RV32-NEXT: vle32.v v16, (a1)
; RV32-NEXT: vle32.v v8, (a2)
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 69
-; RV32-NEXT: mul a1, a1, a2
+; RV32-NEXT: slli a2, a1, 6
+; RV32-NEXT: add a1, a2, a1
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 61
+; RV32-NEXT: li a2, 73
; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl8r.v v0, (a1) # Unknown-size Folded Reload
-; RV32-NEXT: vrgather.vv v8, v0, v24
+; RV32-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
+; RV32-NEXT: vrgather.vv v8, v24, v16
+; RV32-NEXT: vmv1r.v v0, v2
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 53
+; RV32-NEXT: li a2, 49
; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload
+; RV32-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 45
-; RV32-NEXT: mul a1, a1, a2
+; RV32-NEXT: slli a2, a1, 6
+; RV32-NEXT: add a1, a2, a1
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 69
-; RV32-NEXT: mul a1, a1, a2
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload
-; RV32-NEXT: vrgather.vv v8, v24, v16, v0.t
+; RV32-NEXT: vrgather.vv v8, v16, v24, v0.t
; RV32-NEXT: vsetivli zero, 10, e32, m4, tu, ma
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 41
+; RV32-NEXT: li a2, 45
; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
@@ -605,46 +642,40 @@ define {<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>} @load_
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; RV32-NEXT: vse32.v v12, (a1)
; RV32-NEXT: addi a1, a0, 256
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 29
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl4r.v v8, (a2) # Unknown-size Folded Reload
-; RV32-NEXT: vse32.v v8, (a1)
+; RV32-NEXT: vse32.v v4, (a1)
; RV32-NEXT: addi a1, a0, 192
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 37
-; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: slli a3, a2, 5
+; RV32-NEXT: add a2, a3, a2
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: vl4r.v v8, (a2) # Unknown-size Folded Reload
; RV32-NEXT: vse32.v v8, (a1)
; RV32-NEXT: addi a1, a0, 128
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a3, a2, 2
-; RV32-NEXT: add a2, a3, a2
+; RV32-NEXT: li a3, 37
+; RV32-NEXT: mul a2, a2, a3
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: vl4r.v v8, (a2) # Unknown-size Folded Reload
; RV32-NEXT: vse32.v v8, (a1)
; RV32-NEXT: addi a1, a0, 64
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a3, a2, 4
-; RV32-NEXT: add a2, a3, a2
+; RV32-NEXT: li a3, 25
+; RV32-NEXT: mul a2, a2, a3
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: vl4r.v v8, (a2) # Unknown-size Folded Reload
; RV32-NEXT: vse32.v v8, (a1)
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 21
+; RV32-NEXT: li a2, 41
; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vl4r.v v8, (a1) # Unknown-size Folded Reload
; RV32-NEXT: vse32.v v8, (a0)
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 78
+; RV32-NEXT: li a1, 82
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: addi sp, sp, 16
@@ -655,15 +686,15 @@ define {<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>} @load_
; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 90
+; RV64-NEXT: li a3, 84
; RV64-NEXT: mul a2, a2, a3
; RV64-NEXT: sub sp, sp, a2
-; RV64-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0xda, 0x00, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 90 * vlenb
+; RV64-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0xd4, 0x00, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 84 * vlenb
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: addi a2, a1, 256
; RV64-NEXT: vle64.v v16, (a2)
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 57
+; RV64-NEXT: li a3, 52
; RV64-NEXT: mul a2, a2, a3
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 16
@@ -671,14 +702,14 @@ define {<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>} @load_
; RV64-NEXT: addi a2, a1, 128
; RV64-NEXT: vle64.v v8, (a2)
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: slli a3, a2, 6
-; RV64-NEXT: add a2, a3, a2
+; RV64-NEXT: li a3, 60
+; RV64-NEXT: mul a2, a2, a3
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 16
; RV64-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill
; RV64-NEXT: vle64.v v8, (a1)
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 73
+; RV64-NEXT: li a2, 68
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
@@ -686,182 +717,181 @@ define {<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>} @load_
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64-NEXT: vrgather.vi v8, v16, 4
; RV64-NEXT: li a1, 128
-; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
-; RV64-NEXT: vmv.v.x v1, a1
+; RV64-NEXT: vmv.s.x v0, a1
; RV64-NEXT: vsetivli zero, 8, e64, m8, ta, ma
; RV64-NEXT: vslidedown.vi v24, v16, 8
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 49
+; RV64-NEXT: li a2, 44
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vmv1r.v v0, v1
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a2, a1, 5
-; RV64-NEXT: add a1, a2, a1
+; RV64-NEXT: li a2, 24
+; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vs1r.v v1, (a1) # Unknown-size Folded Spill
+; RV64-NEXT: vs1r.v v0, (a1) # Unknown-size Folded Spill
; RV64-NEXT: vrgather.vi v8, v24, 2, v0.t
-; RV64-NEXT: vmv.v.v v4, v8
-; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: li a2, 40
+; RV64-NEXT: mul a1, a1, a2
+; RV64-NEXT: add a1, sp, a1
+; RV64-NEXT: addi a1, a1, 16
+; RV64-NEXT: vs4r.v v8, (a1) # Unknown-size Folded Spill
+; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV64-NEXT: li a1, 6
; RV64-NEXT: vid.v v8
-; RV64-NEXT: vmul.vx v16, v8, a1
+; RV64-NEXT: vmul.vx v24, v8, a1
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 81
+; RV64-NEXT: li a2, 76
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill
+; RV64-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill
; RV64-NEXT: li a1, 56
-; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 73
-; RV64-NEXT: mul a2, a2, a3
-; RV64-NEXT: add a2, sp, a2
-; RV64-NEXT: addi a2, a2, 16
-; RV64-NEXT: vl8r.v v8, (a2) # Unknown-size Folded Reload
-; RV64-NEXT: vrgather.vv v24, v8, v16
-; RV64-NEXT: vadd.vi v8, v16, -16
-; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 41
-; RV64-NEXT: mul a2, a2, a3
-; RV64-NEXT: add a2, sp, a2
-; RV64-NEXT: addi a2, a2, 16
-; RV64-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill
-; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; RV64-NEXT: vmv.v.x v0, a1
+; RV64-NEXT: vmv.s.x v0, a1
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 25
+; RV64-NEXT: li a2, 20
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vs1r.v v0, (a1) # Unknown-size Folded Spill
-; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a2, a1, 6
-; RV64-NEXT: add a1, a2, a1
+; RV64-NEXT: li a2, 68
+; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
+; RV64-NEXT: vrgather.vv v16, v8, v24
+; RV64-NEXT: vadd.vi v8, v24, -16
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 41
+; RV64-NEXT: slli a1, a1, 5
+; RV64-NEXT: add a1, sp, a1
+; RV64-NEXT: addi a1, a1, 16
+; RV64-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: li a2, 60
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload
-; RV64-NEXT: vrgather.vv v24, v8, v16, v0.t
+; RV64-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: slli a1, a1, 5
+; RV64-NEXT: add a1, sp, a1
+; RV64-NEXT: addi a1, a1, 16
+; RV64-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
+; RV64-NEXT: vrgather.vv v16, v8, v24, v0.t
; RV64-NEXT: vsetivli zero, 6, e64, m4, tu, ma
-; RV64-NEXT: vmv.v.v v4, v24
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 29
+; RV64-NEXT: li a2, 40
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vs4r.v v4, (a1) # Unknown-size Folded Spill
-; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
+; RV64-NEXT: vl4r.v v8, (a1) # Unknown-size Folded Reload
+; RV64-NEXT: vmv.v.v v8, v16
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 57
+; RV64-NEXT: li a2, 40
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
-; RV64-NEXT: vrgather.vi v16, v8, 5
-; RV64-NEXT: vmv1r.v v0, v1
+; RV64-NEXT: vs4r.v v8, (a1) # Unknown-size Folded Spill
+; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 49
+; RV64-NEXT: li a2, 52
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
-; RV64-NEXT: vrgather.vi v16, v8, 3, v0.t
+; RV64-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload
+; RV64-NEXT: vrgather.vi v8, v16, 5
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 41
+; RV64-NEXT: li a2, 24
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vs4r.v v16, (a1) # Unknown-size Folded Spill
-; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
+; RV64-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 81
+; RV64-NEXT: li a2, 44
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload
-; RV64-NEXT: vadd.vi v0, v16, 1
+; RV64-NEXT: vrgather.vi v8, v16, 3, v0.t
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 73
-; RV64-NEXT: mul a1, a1, a2
+; RV64-NEXT: slli a1, a1, 5
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
-; RV64-NEXT: vrgather.vv v24, v8, v0
-; RV64-NEXT: vadd.vi v8, v16, -15
+; RV64-NEXT: vs4r.v v8, (a1) # Unknown-size Folded Spill
+; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a2, a1, 4
-; RV64-NEXT: add a1, a2, a1
+; RV64-NEXT: li a2, 76
+; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
+; RV64-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload
+; RV64-NEXT: vadd.vi v0, v16, 1
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 25
+; RV64-NEXT: li a2, 68
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload
+; RV64-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
+; RV64-NEXT: vrgather.vv v8, v24, v0
+; RV64-NEXT: vadd.vi v24, v16, -15
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a2, a1, 6
-; RV64-NEXT: add a1, a2, a1
+; RV64-NEXT: li a2, 20
+; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
+; RV64-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a2, a1, 4
-; RV64-NEXT: add a1, a2, a1
+; RV64-NEXT: li a2, 60
+; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload
-; RV64-NEXT: vrgather.vv v24, v8, v16, v0.t
+; RV64-NEXT: vrgather.vv v8, v16, v24, v0.t
; RV64-NEXT: vsetivli zero, 6, e64, m4, tu, ma
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 41
-; RV64-NEXT: mul a1, a1, a2
+; RV64-NEXT: slli a1, a1, 5
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vl4r.v v8, (a1) # Unknown-size Folded Reload
-; RV64-NEXT: vmv.v.v v8, v24
+; RV64-NEXT: vl4r.v v12, (a1) # Unknown-size Folded Reload
+; RV64-NEXT: vmv.v.v v12, v8
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 41
+; RV64-NEXT: slli a1, a1, 5
+; RV64-NEXT: add a1, sp, a1
+; RV64-NEXT: addi a1, a1, 16
+; RV64-NEXT: vs4r.v v12, (a1) # Unknown-size Folded Spill
+; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: li a2, 76
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vs4r.v v8, (a1) # Unknown-size Folded Spill
-; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
+; RV64-NEXT: vl8r.v v0, (a1) # Unknown-size Folded Reload
+; RV64-NEXT: vadd.vi v8, v0, 2
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 81
+; RV64-NEXT: li a2, 68
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
-; RV64-NEXT: vadd.vi v8, v24, 2
+; RV64-NEXT: vrgather.vv v16, v24, v8
+; RV64-NEXT: li a1, 24
+; RV64-NEXT: vmv.s.x v24, a1
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 73
+; RV64-NEXT: li a2, 12
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vl8r.v v0, (a1) # Unknown-size Folded Reload
-; RV64-NEXT: vrgather.vv v16, v0, v8
-; RV64-NEXT: li a1, 24
-; RV64-NEXT: vadd.vi v8, v24, -14
-; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; RV64-NEXT: vmv.v.x v2, a1
-; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
-; RV64-NEXT: vmv1r.v v0, v2
+; RV64-NEXT: vs1r.v v24, (a1) # Unknown-size Folded Spill
+; RV64-NEXT: vadd.vi v8, v0, -14
+; RV64-NEXT: vmv1r.v v0, v24
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a2, a1, 6
-; RV64-NEXT: add a1, a2, a1
+; RV64-NEXT: li a2, 60
+; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
@@ -869,31 +899,31 @@ define {<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>} @load_
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64-NEXT: vmv.v.i v8, 6
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a2, a1, 2
-; RV64-NEXT: add a1, a2, a1
+; RV64-NEXT: slli a1, a1, 4
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vs4r.v v8, (a1) # Unknown-size Folded Spill
-; RV64-NEXT: vmv.s.x v4, zero
+; RV64-NEXT: vmv.s.x v12, zero
; RV64-NEXT: vsetivli zero, 6, e64, m4, tu, ma
-; RV64-NEXT: vslideup.vi v8, v4, 5
+; RV64-NEXT: addi a1, sp, 16
+; RV64-NEXT: vs4r.v v12, (a1) # Unknown-size Folded Spill
+; RV64-NEXT: vslideup.vi v8, v12, 5
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 57
+; RV64-NEXT: li a2, 52
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vrgather.vv v12, v24, v8
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a2, a1, 5
-; RV64-NEXT: add a1, a2, a1
+; RV64-NEXT: li a2, 24
+; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vl1r.v v1, (a1) # Unknown-size Folded Reload
-; RV64-NEXT: vmv1r.v v0, v1
+; RV64-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 49
+; RV64-NEXT: li a2, 44
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
@@ -902,75 +932,73 @@ define {<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>} @load_
; RV64-NEXT: vsetivli zero, 5, e64, m4, tu, ma
; RV64-NEXT: vmv.v.v v12, v16
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 25
+; RV64-NEXT: li a2, 20
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vs4r.v v12, (a1) # Unknown-size Folded Spill
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 81
+; RV64-NEXT: li a2, 76
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
-; RV64-NEXT: vadd.vi v16, v8, 3
+; RV64-NEXT: vadd.vi v0, v8, 3
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 73
+; RV64-NEXT: li a2, 68
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
-; RV64-NEXT: vrgather.vv v8, v24, v16
-; RV64-NEXT: vmv.v.v v24, v8
+; RV64-NEXT: vrgather.vv v16, v24, v0
+; RV64-NEXT: vadd.vi v8, v8, -13
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 81
+; RV64-NEXT: li a2, 12
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
-; RV64-NEXT: vadd.vi v8, v8, -13
-; RV64-NEXT: vmv1r.v v0, v2
+; RV64-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a2, a1, 6
-; RV64-NEXT: add a1, a2, a1
+; RV64-NEXT: li a2, 60
+; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload
-; RV64-NEXT: vrgather.vv v24, v16, v8, v0.t
+; RV64-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
+; RV64-NEXT: vrgather.vv v16, v24, v8, v0.t
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a2, a1, 3
-; RV64-NEXT: add a1, a2, a1
+; RV64-NEXT: slli a1, a1, 2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill
+; RV64-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64-NEXT: vmv.v.i v12, 7
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a2, a1, 4
-; RV64-NEXT: add a1, a2, a1
+; RV64-NEXT: li a2, 12
+; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vs4r.v v12, (a1) # Unknown-size Folded Spill
; RV64-NEXT: vsetivli zero, 8, e64, m1, ta, ma
-; RV64-NEXT: vmv.v.i v16, 1
+; RV64-NEXT: vmv.v.i v4, 1
; RV64-NEXT: vsetivli zero, 6, e64, m4, tu, ma
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: add a1, sp, a1
-; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vs4r.v v16, (a1) # Unknown-size Folded Spill
-; RV64-NEXT: vslideup.vi v12, v16, 5
+; RV64-NEXT: vslideup.vi v12, v4, 5
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 57
+; RV64-NEXT: li a2, 52
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vrgather.vv v16, v24, v12
-; RV64-NEXT: vmv1r.v v0, v1
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 49
+; RV64-NEXT: li a2, 24
+; RV64-NEXT: mul a1, a1, a2
+; RV64-NEXT: add a1, sp, a1
+; RV64-NEXT: addi a1, a1, 16
+; RV64-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: li a2, 44
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
@@ -978,178 +1006,163 @@ define {<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>} @load_
; RV64-NEXT: vrgather.vi v16, v8, 5, v0.t
; RV64-NEXT: vsetivli zero, 5, e64, m4, tu, ma
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a2, a1, 3
-; RV64-NEXT: add a1, a2, a1
+; RV64-NEXT: slli a1, a1, 2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vmv.v.v v16, v8
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a2, a1, 3
-; RV64-NEXT: add a1, a2, a1
+; RV64-NEXT: slli a1, a1, 2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vs4r.v v16, (a1) # Unknown-size Folded Spill
-; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
+; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 81
+; RV64-NEXT: li a2, 76
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vadd.vi v8, v8, 4
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 73
+; RV64-NEXT: li a2, 68
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vrgather.vv v16, v24, v8
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a2, a1, 5
-; RV64-NEXT: add a1, a2, a1
+; RV64-NEXT: li a2, 24
+; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill
; RV64-NEXT: li a1, 28
-; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 81
-; RV64-NEXT: mul a2, a2, a3
-; RV64-NEXT: add a2, sp, a2
-; RV64-NEXT: addi a2, a2, 16
-; RV64-NEXT: vl8r.v v8, (a2) # Unknown-size Folded Reload
+; RV64-NEXT: vmv.s.x v1, a1
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: li a2, 76
+; RV64-NEXT: mul a1, a1, a2
+; RV64-NEXT: add a1, sp, a1
+; RV64-NEXT: addi a1, a1, 16
+; RV64-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vadd.vi v16, v8, -12
-; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; RV64-NEXT: vmv.v.x v0, a1
-; RV64-NEXT: addi a1, sp, 16
-; RV64-NEXT: vs1r.v v0, (a1) # Unknown-size Folded Spill
-; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
+; RV64-NEXT: vmv1r.v v0, v1
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a2, a1, 6
-; RV64-NEXT: add a1, a2, a1
+; RV64-NEXT: li a2, 60
+; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a2, a1, 5
-; RV64-NEXT: add a1, a2, a1
+; RV64-NEXT: li a2, 24
+; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vrgather.vv v8, v24, v16, v0.t
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a2, a1, 5
-; RV64-NEXT: add a1, a2, a1
+; RV64-NEXT: li a2, 24
+; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; RV64-NEXT: vsetivli zero, 7, e64, m4, tu, ma
+; RV64-NEXT: addi a1, sp, 16
+; RV64-NEXT: vl4r.v v8, (a1) # Unknown-size Folded Reload
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a2, a1, 2
-; RV64-NEXT: add a1, a2, a1
+; RV64-NEXT: slli a1, a1, 4
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl4r.v v24, (a1) # Unknown-size Folded Reload
-; RV64-NEXT: vslideup.vi v24, v4, 6
-; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
+; RV64-NEXT: vslideup.vi v24, v8, 6
+; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: li a1, 192
-; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 57
-; RV64-NEXT: mul a2, a2, a3
-; RV64-NEXT: add a2, sp, a2
-; RV64-NEXT: addi a2, a2, 16
-; RV64-NEXT: vl8r.v v8, (a2) # Unknown-size Folded Reload
-; RV64-NEXT: vrgather.vi v28, v8, 2
-; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
-; RV64-NEXT: vmv.v.x v0, a1
+; RV64-NEXT: vmv.s.x v2, a1
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a2, a1, 2
-; RV64-NEXT: add a1, a2, a1
+; RV64-NEXT: li a2, 52
+; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vs1r.v v0, (a1) # Unknown-size Folded Spill
-; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
+; RV64-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
+; RV64-NEXT: vrgather.vi v16, v8, 2
+; RV64-NEXT: vmv1r.v v0, v2
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 49
+; RV64-NEXT: li a2, 44
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
-; RV64-NEXT: vmv4r.v v12, v28
+; RV64-NEXT: vmv.v.v v12, v16
; RV64-NEXT: vrgather.vv v12, v8, v24, v0.t
; RV64-NEXT: vsetivli zero, 5, e64, m4, tu, ma
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a2, a1, 5
-; RV64-NEXT: add a1, a2, a1
+; RV64-NEXT: li a2, 24
+; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
-; RV64-NEXT: vmv.v.v v12, v24
+; RV64-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload
+; RV64-NEXT: vmv.v.v v12, v16
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a2, a1, 5
-; RV64-NEXT: add a1, a2, a1
+; RV64-NEXT: li a2, 24
+; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vs4r.v v12, (a1) # Unknown-size Folded Spill
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 81
+; RV64-NEXT: li a2, 76
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vl8r.v v0, (a1) # Unknown-size Folded Reload
-; RV64-NEXT: vadd.vi v24, v0, 5
+; RV64-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
+; RV64-NEXT: vadd.vi v16, v8, 5
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 73
+; RV64-NEXT: li a2, 68
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
-; RV64-NEXT: vrgather.vv v16, v8, v24
-; RV64-NEXT: vadd.vi v24, v0, -11
-; RV64-NEXT: addi a1, sp, 16
-; RV64-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload
+; RV64-NEXT: vrgather.vv v24, v8, v16
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a2, a1, 6
-; RV64-NEXT: add a1, a2, a1
+; RV64-NEXT: li a2, 76
+; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
-; RV64-NEXT: vrgather.vv v16, v8, v24, v0.t
+; RV64-NEXT: vadd.vi v16, v8, -11
+; RV64-NEXT: vmv1r.v v0, v1
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 81
+; RV64-NEXT: li a2, 60
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill
-; RV64-NEXT: vsetivli zero, 7, e64, m4, tu, ma
+; RV64-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
+; RV64-NEXT: vrgather.vv v24, v8, v16, v0.t
; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: li a2, 76
+; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vl4r.v v8, (a1) # Unknown-size Folded Reload
+; RV64-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill
+; RV64-NEXT: vsetivli zero, 7, e64, m4, tu, ma
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a2, a1, 4
-; RV64-NEXT: add a1, a2, a1
+; RV64-NEXT: li a2, 12
+; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl4r.v v24, (a1) # Unknown-size Folded Reload
-; RV64-NEXT: vslideup.vi v24, v8, 6
+; RV64-NEXT: vslideup.vi v24, v4, 6
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 57
+; RV64-NEXT: li a2, 52
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vrgather.vi v12, v8, 3
+; RV64-NEXT: vmv1r.v v0, v2
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a2, a1, 2
-; RV64-NEXT: add a1, a2, a1
-; RV64-NEXT: add a1, sp, a1
-; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 49
+; RV64-NEXT: li a2, 44
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
@@ -1157,7 +1170,7 @@ define {<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>} @load_
; RV64-NEXT: vrgather.vv v12, v16, v24, v0.t
; RV64-NEXT: vsetivli zero, 5, e64, m4, tu, ma
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 81
+; RV64-NEXT: li a2, 76
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
@@ -1168,23 +1181,22 @@ define {<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>} @load_
; RV64-NEXT: vse64.v v12, (a1)
; RV64-NEXT: addi a1, a0, 256
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: slli a3, a2, 5
-; RV64-NEXT: add a2, a3, a2
+; RV64-NEXT: li a3, 24
+; RV64-NEXT: mul a2, a2, a3
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 16
; RV64-NEXT: vl4r.v v8, (a2) # Unknown-size Folded Reload
; RV64-NEXT: vse64.v v8, (a1)
; RV64-NEXT: addi a1, a0, 192
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: slli a3, a2, 3
-; RV64-NEXT: add a2, a3, a2
+; RV64-NEXT: slli a2, a2, 2
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 16
; RV64-NEXT: vl4r.v v8, (a2) # Unknown-size Folded Reload
; RV64-NEXT: vse64.v v8, (a1)
; RV64-NEXT: addi a1, a0, 128
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 25
+; RV64-NEXT: li a3, 20
; RV64-NEXT: mul a2, a2, a3
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 16
@@ -1192,21 +1204,20 @@ define {<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>} @load_
; RV64-NEXT: vse64.v v8, (a1)
; RV64-NEXT: addi a1, a0, 64
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 41
-; RV64-NEXT: mul a2, a2, a3
+; RV64-NEXT: slli a2, a2, 5
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 16
; RV64-NEXT: vl4r.v v8, (a2) # Unknown-size Folded Reload
; RV64-NEXT: vse64.v v8, (a1)
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 29
+; RV64-NEXT: li a2, 40
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl4r.v v8, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vse64.v v8, (a0)
; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: li a1, 90
+; RV64-NEXT: li a1, 84
; RV64-NEXT: mul a0, a0, a1
; RV64-NEXT: add sp, sp, a0
; RV64-NEXT: addi sp, sp, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
index 0d0c927d068df2..ba577e6a249754 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
@@ -16,7 +16,7 @@ define <1 x i1> @buildvec_mask_nonconst_v1i1(i1 %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
-; CHECK-NEXT: vmv.v.x v8, a0
+; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
;
@@ -24,7 +24,7 @@ define <1 x i1> @buildvec_mask_nonconst_v1i1(i1 %x) {
; ZVE32F: # %bb.0:
; ZVE32F-NEXT: andi a0, a0, 1
; ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; ZVE32F-NEXT: vmv.v.x v8, a0
+; ZVE32F-NEXT: vmv.s.x v8, a0
; ZVE32F-NEXT: vmsne.vi v0, v8, 0
; ZVE32F-NEXT: ret
%1 = insertelement <1 x i1> poison, i1 %x, i32 0
@@ -36,7 +36,7 @@ define <1 x i1> @buildvec_mask_optsize_nonconst_v1i1(i1 %x) optsize {
; CHECK: # %bb.0:
; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
-; CHECK-NEXT: vmv.v.x v8, a0
+; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
;
@@ -44,7 +44,7 @@ define <1 x i1> @buildvec_mask_optsize_nonconst_v1i1(i1 %x) optsize {
; ZVE32F: # %bb.0:
; ZVE32F-NEXT: andi a0, a0, 1
; ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; ZVE32F-NEXT: vmv.v.x v8, a0
+; ZVE32F-NEXT: vmv.s.x v8, a0
; ZVE32F-NEXT: vmsne.vi v0, v8, 0
; ZVE32F-NEXT: ret
%1 = insertelement <1 x i1> poison, i1 %x, i32 0
@@ -236,14 +236,14 @@ define <8 x i1> @buildvec_mask_v8i1() {
; CHECK: # %bb.0:
; CHECK-NEXT: li a0, 182
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
-; CHECK-NEXT: vmv.v.x v0, a0
+; CHECK-NEXT: vmv.s.x v0, a0
; CHECK-NEXT: ret
;
; ZVE32F-LABEL: buildvec_mask_v8i1:
; ZVE32F: # %bb.0:
; ZVE32F-NEXT: li a0, 182
; ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; ZVE32F-NEXT: vmv.v.x v0, a0
+; ZVE32F-NEXT: vmv.s.x v0, a0
; ZVE32F-NEXT: ret
ret <8 x i1> <i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1>
}
@@ -253,7 +253,7 @@ define <8 x i1> @buildvec_mask_nonconst_v8i1(i1 %x, i1 %y) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: li a2, 19
-; CHECK-NEXT: vmv.v.x v0, a2
+; CHECK-NEXT: vmv.s.x v0, a2
; CHECK-NEXT: vmv.v.x v8, a1
; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: vand.vi v8, v8, 1
@@ -264,7 +264,7 @@ define <8 x i1> @buildvec_mask_nonconst_v8i1(i1 %x, i1 %y) {
; ZVE32F: # %bb.0:
; ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; ZVE32F-NEXT: li a2, 19
-; ZVE32F-NEXT: vmv.v.x v0, a2
+; ZVE32F-NEXT: vmv.s.x v0, a2
; ZVE32F-NEXT: vmv.v.x v8, a1
; ZVE32F-NEXT: vmerge.vxm v8, v8, a0, v0
; ZVE32F-NEXT: vand.vi v8, v8, 1
@@ -413,14 +413,14 @@ define <10 x i1> @buildvec_mask_v10i1() {
; CHECK: # %bb.0:
; CHECK-NEXT: li a0, 949
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; CHECK-NEXT: vmv.v.x v0, a0
+; CHECK-NEXT: vmv.s.x v0, a0
; CHECK-NEXT: ret
;
; ZVE32F-LABEL: buildvec_mask_v10i1:
; ZVE32F: # %bb.0:
; ZVE32F-NEXT: li a0, 949
; ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
-; ZVE32F-NEXT: vmv.v.x v0, a0
+; ZVE32F-NEXT: vmv.s.x v0, a0
; ZVE32F-NEXT: ret
ret <10 x i1> <i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 1>
}
@@ -431,7 +431,7 @@ define <16 x i1> @buildvec_mask_v16i1() {
; CHECK-RV32-NEXT: lui a0, 11
; CHECK-RV32-NEXT: addi a0, a0, 1718
; CHECK-RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; CHECK-RV32-NEXT: vmv.v.x v0, a0
+; CHECK-RV32-NEXT: vmv.s.x v0, a0
; CHECK-RV32-NEXT: ret
;
; CHECK-RV64-LABEL: buildvec_mask_v16i1:
@@ -439,7 +439,7 @@ define <16 x i1> @buildvec_mask_v16i1() {
; CHECK-RV64-NEXT: lui a0, 11
; CHECK-RV64-NEXT: addiw a0, a0, 1718
; CHECK-RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; CHECK-RV64-NEXT: vmv.v.x v0, a0
+; CHECK-RV64-NEXT: vmv.s.x v0, a0
; CHECK-RV64-NEXT: ret
ret <16 x i1> <i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1>
}
@@ -449,14 +449,14 @@ define <16 x i1> @buildvec_mask_v16i1_undefs() {
; CHECK: # %bb.0:
; CHECK-NEXT: li a0, 1722
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; CHECK-NEXT: vmv.v.x v0, a0
+; CHECK-NEXT: vmv.s.x v0, a0
; CHECK-NEXT: ret
;
; ZVE32F-LABEL: buildvec_mask_v16i1_undefs:
; ZVE32F: # %bb.0:
; ZVE32F-NEXT: li a0, 1722
; ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
-; ZVE32F-NEXT: vmv.v.x v0, a0
+; ZVE32F-NEXT: vmv.s.x v0, a0
; ZVE32F-NEXT: ret
ret <16 x i1> <i1 undef, i1 1, i1 undef, i1 1, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 undef, i1 undef, i1 undef, i1 undef, i1 undef>
}
@@ -466,20 +466,20 @@ define <32 x i1> @buildvec_mask_v32i1() {
; RV32-LMULMAX1: # %bb.0:
; RV32-LMULMAX1-NEXT: li a0, 1776
; RV32-LMULMAX1-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; RV32-LMULMAX1-NEXT: vmv.v.x v0, a0
+; RV32-LMULMAX1-NEXT: vmv.s.x v0, a0
; RV32-LMULMAX1-NEXT: lui a0, 11
; RV32-LMULMAX1-NEXT: addi a0, a0, 1718
-; RV32-LMULMAX1-NEXT: vmv.v.x v8, a0
+; RV32-LMULMAX1-NEXT: vmv.s.x v8, a0
; RV32-LMULMAX1-NEXT: ret
;
; RV64-LMULMAX1-LABEL: buildvec_mask_v32i1:
; RV64-LMULMAX1: # %bb.0:
; RV64-LMULMAX1-NEXT: li a0, 1776
; RV64-LMULMAX1-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; RV64-LMULMAX1-NEXT: vmv.v.x v0, a0
+; RV64-LMULMAX1-NEXT: vmv.s.x v0, a0
; RV64-LMULMAX1-NEXT: lui a0, 11
; RV64-LMULMAX1-NEXT: addiw a0, a0, 1718
-; RV64-LMULMAX1-NEXT: vmv.v.x v8, a0
+; RV64-LMULMAX1-NEXT: vmv.s.x v8, a0
; RV64-LMULMAX1-NEXT: ret
;
; RV32-LMULMAX2-LABEL: buildvec_mask_v32i1:
@@ -487,7 +487,7 @@ define <32 x i1> @buildvec_mask_v32i1() {
; RV32-LMULMAX2-NEXT: lui a0, 748384
; RV32-LMULMAX2-NEXT: addi a0, a0, 1776
; RV32-LMULMAX2-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; RV32-LMULMAX2-NEXT: vmv.v.x v0, a0
+; RV32-LMULMAX2-NEXT: vmv.s.x v0, a0
; RV32-LMULMAX2-NEXT: ret
;
; RV64-LMULMAX2-LABEL: buildvec_mask_v32i1:
@@ -495,7 +495,7 @@ define <32 x i1> @buildvec_mask_v32i1() {
; RV64-LMULMAX2-NEXT: lui a0, 748384
; RV64-LMULMAX2-NEXT: addiw a0, a0, 1776
; RV64-LMULMAX2-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; RV64-LMULMAX2-NEXT: vmv.v.x v0, a0
+; RV64-LMULMAX2-NEXT: vmv.s.x v0, a0
; RV64-LMULMAX2-NEXT: ret
;
; RV32-LMULMAX4-LABEL: buildvec_mask_v32i1:
@@ -503,7 +503,7 @@ define <32 x i1> @buildvec_mask_v32i1() {
; RV32-LMULMAX4-NEXT: lui a0, 748384
; RV32-LMULMAX4-NEXT: addi a0, a0, 1776
; RV32-LMULMAX4-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; RV32-LMULMAX4-NEXT: vmv.v.x v0, a0
+; RV32-LMULMAX4-NEXT: vmv.s.x v0, a0
; RV32-LMULMAX4-NEXT: ret
;
; RV64-LMULMAX4-LABEL: buildvec_mask_v32i1:
@@ -511,7 +511,7 @@ define <32 x i1> @buildvec_mask_v32i1() {
; RV64-LMULMAX4-NEXT: lui a0, 748384
; RV64-LMULMAX4-NEXT: addiw a0, a0, 1776
; RV64-LMULMAX4-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; RV64-LMULMAX4-NEXT: vmv.v.x v0, a0
+; RV64-LMULMAX4-NEXT: vmv.s.x v0, a0
; RV64-LMULMAX4-NEXT: ret
;
; RV32-LMULMAX8-LABEL: buildvec_mask_v32i1:
@@ -519,7 +519,7 @@ define <32 x i1> @buildvec_mask_v32i1() {
; RV32-LMULMAX8-NEXT: lui a0, 748384
; RV32-LMULMAX8-NEXT: addi a0, a0, 1776
; RV32-LMULMAX8-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; RV32-LMULMAX8-NEXT: vmv.v.x v0, a0
+; RV32-LMULMAX8-NEXT: vmv.s.x v0, a0
; RV32-LMULMAX8-NEXT: ret
;
; RV64-LMULMAX8-LABEL: buildvec_mask_v32i1:
@@ -527,7 +527,7 @@ define <32 x i1> @buildvec_mask_v32i1() {
; RV64-LMULMAX8-NEXT: lui a0, 748384
; RV64-LMULMAX8-NEXT: addiw a0, a0, 1776
; RV64-LMULMAX8-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; RV64-LMULMAX8-NEXT: vmv.v.x v0, a0
+; RV64-LMULMAX8-NEXT: vmv.s.x v0, a0
; RV64-LMULMAX8-NEXT: ret
ret <32 x i1> <i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1>
}
@@ -537,13 +537,13 @@ define <64 x i1> @buildvec_mask_v64i1() {
; RV32-LMULMAX1: # %bb.0:
; RV32-LMULMAX1-NEXT: li a0, 1776
; RV32-LMULMAX1-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; RV32-LMULMAX1-NEXT: vmv.v.x v0, a0
+; RV32-LMULMAX1-NEXT: vmv.s.x v0, a0
; RV32-LMULMAX1-NEXT: lui a0, 4
; RV32-LMULMAX1-NEXT: addi a0, a0, -1793
-; RV32-LMULMAX1-NEXT: vmv.v.x v9, a0
+; RV32-LMULMAX1-NEXT: vmv.s.x v9, a0
; RV32-LMULMAX1-NEXT: lui a0, 11
; RV32-LMULMAX1-NEXT: addi a0, a0, 1718
-; RV32-LMULMAX1-NEXT: vmv.v.x v8, a0
+; RV32-LMULMAX1-NEXT: vmv.s.x v8, a0
; RV32-LMULMAX1-NEXT: vmv1r.v v10, v8
; RV32-LMULMAX1-NEXT: ret
;
@@ -551,13 +551,13 @@ define <64 x i1> @buildvec_mask_v64i1() {
; RV64-LMULMAX1: # %bb.0:
; RV64-LMULMAX1-NEXT: li a0, 1776
; RV64-LMULMAX1-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; RV64-LMULMAX1-NEXT: vmv.v.x v0, a0
+; RV64-LMULMAX1-NEXT: vmv.s.x v0, a0
; RV64-LMULMAX1-NEXT: lui a0, 4
; RV64-LMULMAX1-NEXT: addiw a0, a0, -1793
-; RV64-LMULMAX1-NEXT: vmv.v.x v9, a0
+; RV64-LMULMAX1-NEXT: vmv.s.x v9, a0
; RV64-LMULMAX1-NEXT: lui a0, 11
; RV64-LMULMAX1-NEXT: addiw a0, a0, 1718
-; RV64-LMULMAX1-NEXT: vmv.v.x v8, a0
+; RV64-LMULMAX1-NEXT: vmv.s.x v8, a0
; RV64-LMULMAX1-NEXT: vmv1r.v v10, v8
; RV64-LMULMAX1-NEXT: ret
;
@@ -566,10 +566,10 @@ define <64 x i1> @buildvec_mask_v64i1() {
; RV32-LMULMAX2-NEXT: lui a0, 748384
; RV32-LMULMAX2-NEXT: addi a0, a0, 1776
; RV32-LMULMAX2-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; RV32-LMULMAX2-NEXT: vmv.v.x v0, a0
+; RV32-LMULMAX2-NEXT: vmv.s.x v0, a0
; RV32-LMULMAX2-NEXT: lui a0, 748388
; RV32-LMULMAX2-NEXT: addi a0, a0, -1793
-; RV32-LMULMAX2-NEXT: vmv.v.x v8, a0
+; RV32-LMULMAX2-NEXT: vmv.s.x v8, a0
; RV32-LMULMAX2-NEXT: ret
;
; RV64-LMULMAX2-LABEL: buildvec_mask_v64i1:
@@ -577,10 +577,10 @@ define <64 x i1> @buildvec_mask_v64i1() {
; RV64-LMULMAX2-NEXT: lui a0, 748384
; RV64-LMULMAX2-NEXT: addiw a0, a0, 1776
; RV64-LMULMAX2-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; RV64-LMULMAX2-NEXT: vmv.v.x v0, a0
+; RV64-LMULMAX2-NEXT: vmv.s.x v0, a0
; RV64-LMULMAX2-NEXT: lui a0, 748388
; RV64-LMULMAX2-NEXT: addiw a0, a0, -1793
-; RV64-LMULMAX2-NEXT: vmv.v.x v8, a0
+; RV64-LMULMAX2-NEXT: vmv.s.x v8, a0
; RV64-LMULMAX2-NEXT: ret
;
; RV32-LMULMAX4-LABEL: buildvec_mask_v64i1:
@@ -630,19 +630,19 @@ define <128 x i1> @buildvec_mask_v128i1() {
; RV32-LMULMAX1: # %bb.0:
; RV32-LMULMAX1-NEXT: li a0, 1776
; RV32-LMULMAX1-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; RV32-LMULMAX1-NEXT: vmv.v.x v0, a0
+; RV32-LMULMAX1-NEXT: vmv.s.x v0, a0
; RV32-LMULMAX1-NEXT: lui a0, 11
; RV32-LMULMAX1-NEXT: addi a0, a0, 1718
-; RV32-LMULMAX1-NEXT: vmv.v.x v8, a0
+; RV32-LMULMAX1-NEXT: vmv.s.x v8, a0
; RV32-LMULMAX1-NEXT: lui a0, 8
; RV32-LMULMAX1-NEXT: addi a0, a0, 1718
-; RV32-LMULMAX1-NEXT: vmv.v.x v12, a0
+; RV32-LMULMAX1-NEXT: vmv.s.x v12, a0
; RV32-LMULMAX1-NEXT: lui a0, 4
; RV32-LMULMAX1-NEXT: addi a0, a0, -1793
-; RV32-LMULMAX1-NEXT: vmv.v.x v9, a0
+; RV32-LMULMAX1-NEXT: vmv.s.x v9, a0
; RV32-LMULMAX1-NEXT: lui a0, 14
; RV32-LMULMAX1-NEXT: addi a0, a0, 1722
-; RV32-LMULMAX1-NEXT: vmv.v.x v14, a0
+; RV32-LMULMAX1-NEXT: vmv.s.x v14, a0
; RV32-LMULMAX1-NEXT: vmv1r.v v10, v8
; RV32-LMULMAX1-NEXT: vmv1r.v v11, v0
; RV32-LMULMAX1-NEXT: vmv1r.v v13, v9
@@ -652,19 +652,19 @@ define <128 x i1> @buildvec_mask_v128i1() {
; RV64-LMULMAX1: # %bb.0:
; RV64-LMULMAX1-NEXT: li a0, 1776
; RV64-LMULMAX1-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; RV64-LMULMAX1-NEXT: vmv.v.x v0, a0
+; RV64-LMULMAX1-NEXT: vmv.s.x v0, a0
; RV64-LMULMAX1-NEXT: lui a0, 11
; RV64-LMULMAX1-NEXT: addiw a0, a0, 1718
-; RV64-LMULMAX1-NEXT: vmv.v.x v8, a0
+; RV64-LMULMAX1-NEXT: vmv.s.x v8, a0
; RV64-LMULMAX1-NEXT: lui a0, 8
; RV64-LMULMAX1-NEXT: addiw a0, a0, 1718
-; RV64-LMULMAX1-NEXT: vmv.v.x v12, a0
+; RV64-LMULMAX1-NEXT: vmv.s.x v12, a0
; RV64-LMULMAX1-NEXT: lui a0, 4
; RV64-LMULMAX1-NEXT: addiw a0, a0, -1793
-; RV64-LMULMAX1-NEXT: vmv.v.x v9, a0
+; RV64-LMULMAX1-NEXT: vmv.s.x v9, a0
; RV64-LMULMAX1-NEXT: lui a0, 14
; RV64-LMULMAX1-NEXT: addiw a0, a0, 1722
-; RV64-LMULMAX1-NEXT: vmv.v.x v14, a0
+; RV64-LMULMAX1-NEXT: vmv.s.x v14, a0
; RV64-LMULMAX1-NEXT: vmv1r.v v10, v8
; RV64-LMULMAX1-NEXT: vmv1r.v v11, v0
; RV64-LMULMAX1-NEXT: vmv1r.v v13, v9
@@ -675,16 +675,16 @@ define <128 x i1> @buildvec_mask_v128i1() {
; RV32-LMULMAX2-NEXT: lui a0, 748384
; RV32-LMULMAX2-NEXT: addi a0, a0, 1776
; RV32-LMULMAX2-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; RV32-LMULMAX2-NEXT: vmv.v.x v0, a0
+; RV32-LMULMAX2-NEXT: vmv.s.x v0, a0
; RV32-LMULMAX2-NEXT: lui a0, 748388
; RV32-LMULMAX2-NEXT: addi a0, a0, -1793
-; RV32-LMULMAX2-NEXT: vmv.v.x v8, a0
+; RV32-LMULMAX2-NEXT: vmv.s.x v8, a0
; RV32-LMULMAX2-NEXT: lui a0, 551776
; RV32-LMULMAX2-NEXT: addi a0, a0, 1776
-; RV32-LMULMAX2-NEXT: vmv.v.x v9, a0
+; RV32-LMULMAX2-NEXT: vmv.s.x v9, a0
; RV32-LMULMAX2-NEXT: lui a0, 945060
; RV32-LMULMAX2-NEXT: addi a0, a0, -1793
-; RV32-LMULMAX2-NEXT: vmv.v.x v10, a0
+; RV32-LMULMAX2-NEXT: vmv.s.x v10, a0
; RV32-LMULMAX2-NEXT: ret
;
; RV64-LMULMAX2-LABEL: buildvec_mask_v128i1:
@@ -692,16 +692,16 @@ define <128 x i1> @buildvec_mask_v128i1() {
; RV64-LMULMAX2-NEXT: lui a0, 748384
; RV64-LMULMAX2-NEXT: addiw a0, a0, 1776
; RV64-LMULMAX2-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; RV64-LMULMAX2-NEXT: vmv.v.x v0, a0
+; RV64-LMULMAX2-NEXT: vmv.s.x v0, a0
; RV64-LMULMAX2-NEXT: lui a0, 748388
; RV64-LMULMAX2-NEXT: addiw a0, a0, -1793
-; RV64-LMULMAX2-NEXT: vmv.v.x v8, a0
+; RV64-LMULMAX2-NEXT: vmv.s.x v8, a0
; RV64-LMULMAX2-NEXT: lui a0, 551776
; RV64-LMULMAX2-NEXT: addiw a0, a0, 1776
-; RV64-LMULMAX2-NEXT: vmv.v.x v9, a0
+; RV64-LMULMAX2-NEXT: vmv.s.x v9, a0
; RV64-LMULMAX2-NEXT: lui a0, 945060
; RV64-LMULMAX2-NEXT: addiw a0, a0, -1793
-; RV64-LMULMAX2-NEXT: vmv.v.x v10, a0
+; RV64-LMULMAX2-NEXT: vmv.s.x v10, a0
; RV64-LMULMAX2-NEXT: ret
;
; RV32-LMULMAX4-LABEL: buildvec_mask_v128i1:
@@ -770,19 +770,19 @@ define <128 x i1> @buildvec_mask_optsize_v128i1() optsize {
; RV32-LMULMAX1: # %bb.0:
; RV32-LMULMAX1-NEXT: li a0, 1776
; RV32-LMULMAX1-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; RV32-LMULMAX1-NEXT: vmv.v.x v0, a0
+; RV32-LMULMAX1-NEXT: vmv.s.x v0, a0
; RV32-LMULMAX1-NEXT: lui a0, 11
; RV32-LMULMAX1-NEXT: addi a0, a0, 1718
-; RV32-LMULMAX1-NEXT: vmv.v.x v8, a0
+; RV32-LMULMAX1-NEXT: vmv.s.x v8, a0
; RV32-LMULMAX1-NEXT: lui a0, 8
; RV32-LMULMAX1-NEXT: addi a0, a0, 1718
-; RV32-LMULMAX1-NEXT: vmv.v.x v12, a0
+; RV32-LMULMAX1-NEXT: vmv.s.x v12, a0
; RV32-LMULMAX1-NEXT: lui a0, 4
; RV32-LMULMAX1-NEXT: addi a0, a0, -1793
-; RV32-LMULMAX1-NEXT: vmv.v.x v9, a0
+; RV32-LMULMAX1-NEXT: vmv.s.x v9, a0
; RV32-LMULMAX1-NEXT: lui a0, 14
; RV32-LMULMAX1-NEXT: addi a0, a0, 1722
-; RV32-LMULMAX1-NEXT: vmv.v.x v14, a0
+; RV32-LMULMAX1-NEXT: vmv.s.x v14, a0
; RV32-LMULMAX1-NEXT: vmv1r.v v10, v8
; RV32-LMULMAX1-NEXT: vmv1r.v v11, v0
; RV32-LMULMAX1-NEXT: vmv1r.v v13, v9
@@ -792,19 +792,19 @@ define <128 x i1> @buildvec_mask_optsize_v128i1() optsize {
; RV64-LMULMAX1: # %bb.0:
; RV64-LMULMAX1-NEXT: li a0, 1776
; RV64-LMULMAX1-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; RV64-LMULMAX1-NEXT: vmv.v.x v0, a0
+; RV64-LMULMAX1-NEXT: vmv.s.x v0, a0
; RV64-LMULMAX1-NEXT: lui a0, 11
; RV64-LMULMAX1-NEXT: addiw a0, a0, 1718
-; RV64-LMULMAX1-NEXT: vmv.v.x v8, a0
+; RV64-LMULMAX1-NEXT: vmv.s.x v8, a0
; RV64-LMULMAX1-NEXT: lui a0, 8
; RV64-LMULMAX1-NEXT: addiw a0, a0, 1718
-; RV64-LMULMAX1-NEXT: vmv.v.x v12, a0
+; RV64-LMULMAX1-NEXT: vmv.s.x v12, a0
; RV64-LMULMAX1-NEXT: lui a0, 4
; RV64-LMULMAX1-NEXT: addiw a0, a0, -1793
-; RV64-LMULMAX1-NEXT: vmv.v.x v9, a0
+; RV64-LMULMAX1-NEXT: vmv.s.x v9, a0
; RV64-LMULMAX1-NEXT: lui a0, 14
; RV64-LMULMAX1-NEXT: addiw a0, a0, 1722
-; RV64-LMULMAX1-NEXT: vmv.v.x v14, a0
+; RV64-LMULMAX1-NEXT: vmv.s.x v14, a0
; RV64-LMULMAX1-NEXT: vmv1r.v v10, v8
; RV64-LMULMAX1-NEXT: vmv1r.v v11, v0
; RV64-LMULMAX1-NEXT: vmv1r.v v13, v9
@@ -815,16 +815,16 @@ define <128 x i1> @buildvec_mask_optsize_v128i1() optsize {
; RV32-LMULMAX2-NEXT: lui a0, 748384
; RV32-LMULMAX2-NEXT: addi a0, a0, 1776
; RV32-LMULMAX2-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; RV32-LMULMAX2-NEXT: vmv.v.x v0, a0
+; RV32-LMULMAX2-NEXT: vmv.s.x v0, a0
; RV32-LMULMAX2-NEXT: lui a0, 748388
; RV32-LMULMAX2-NEXT: addi a0, a0, -1793
-; RV32-LMULMAX2-NEXT: vmv.v.x v8, a0
+; RV32-LMULMAX2-NEXT: vmv.s.x v8, a0
; RV32-LMULMAX2-NEXT: lui a0, 551776
; RV32-LMULMAX2-NEXT: addi a0, a0, 1776
-; RV32-LMULMAX2-NEXT: vmv.v.x v9, a0
+; RV32-LMULMAX2-NEXT: vmv.s.x v9, a0
; RV32-LMULMAX2-NEXT: lui a0, 945060
; RV32-LMULMAX2-NEXT: addi a0, a0, -1793
-; RV32-LMULMAX2-NEXT: vmv.v.x v10, a0
+; RV32-LMULMAX2-NEXT: vmv.s.x v10, a0
; RV32-LMULMAX2-NEXT: ret
;
; RV64-LMULMAX2-LABEL: buildvec_mask_optsize_v128i1:
@@ -832,16 +832,16 @@ define <128 x i1> @buildvec_mask_optsize_v128i1() optsize {
; RV64-LMULMAX2-NEXT: lui a0, 748384
; RV64-LMULMAX2-NEXT: addiw a0, a0, 1776
; RV64-LMULMAX2-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; RV64-LMULMAX2-NEXT: vmv.v.x v0, a0
+; RV64-LMULMAX2-NEXT: vmv.s.x v0, a0
; RV64-LMULMAX2-NEXT: lui a0, 748388
; RV64-LMULMAX2-NEXT: addiw a0, a0, -1793
-; RV64-LMULMAX2-NEXT: vmv.v.x v8, a0
+; RV64-LMULMAX2-NEXT: vmv.s.x v8, a0
; RV64-LMULMAX2-NEXT: lui a0, 551776
; RV64-LMULMAX2-NEXT: addiw a0, a0, 1776
-; RV64-LMULMAX2-NEXT: vmv.v.x v9, a0
+; RV64-LMULMAX2-NEXT: vmv.s.x v9, a0
; RV64-LMULMAX2-NEXT: lui a0, 945060
; RV64-LMULMAX2-NEXT: addiw a0, a0, -1793
-; RV64-LMULMAX2-NEXT: vmv.v.x v10, a0
+; RV64-LMULMAX2-NEXT: vmv.s.x v10, a0
; RV64-LMULMAX2-NEXT: ret
;
; RV32-LMULMAX4-LABEL: buildvec_mask_optsize_v128i1:
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll
index dd587de75d97d8..cf6440f09a336f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll
@@ -26,11 +26,11 @@ define void @splat_zeros_v2i1(ptr %x) {
define void @splat_v1i1(ptr %x, i1 %y) {
; CHECK-LABEL: splat_v1i1:
; CHECK: # %bb.0:
-; CHECK-NEXT: andi a1, a1, 1
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
-; CHECK-NEXT: vmv.v.x v8, a1
+; CHECK-NEXT: andi a1, a1, 1
+; CHECK-NEXT: vmv.s.x v8, a1
; CHECK-NEXT: vmsne.vi v0, v8, 0
-; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmv.s.x v8, zero
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vmv.v.i v9, 0
@@ -52,9 +52,9 @@ define void @splat_v1i1_icmp(ptr %x, i32 signext %y, i32 signext %z) {
; CHECK-NEXT: xor a1, a1, a2
; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
-; CHECK-NEXT: vmv.v.x v8, a1
+; CHECK-NEXT: vmv.s.x v8, a1
; CHECK-NEXT: vmsne.vi v0, v8, 0
-; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmv.s.x v8, zero
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vmv.v.i v9, 0
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
index 52d37d7f4b7afe..6808656449ca85 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
@@ -1425,7 +1425,7 @@ define i8 @vpreduce_mul_v1i8(i8 %s, <1 x i8> %v, <1 x i1> %m, i32 zeroext %evl)
; RV32-NEXT: .cfi_offset ra, -4
; RV32-NEXT: mv a2, a0
; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; RV32-NEXT: vmv.v.x v9, a1
+; RV32-NEXT: vmv.s.x v9, a1
; RV32-NEXT: vmsne.vi v9, v9, 0
; RV32-NEXT: vmand.mm v0, v9, v0
; RV32-NEXT: vmv.v.i v9, 1
@@ -1446,7 +1446,7 @@ define i8 @vpreduce_mul_v1i8(i8 %s, <1 x i8> %v, <1 x i1> %m, i32 zeroext %evl)
; RV64-NEXT: .cfi_offset ra, -8
; RV64-NEXT: mv a2, a0
; RV64-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; RV64-NEXT: vmv.v.x v9, a1
+; RV64-NEXT: vmv.s.x v9, a1
; RV64-NEXT: vmsne.vi v9, v9, 0
; RV64-NEXT: vmand.mm v0, v9, v0
; RV64-NEXT: vmv.v.i v9, 1
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-int.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-int.ll
index 4931444c74be2f..adbbf9181b09bd 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-int.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-int.ll
@@ -8,7 +8,7 @@ define <1 x i1> @select_v1i1(i1 zeroext %c, <1 x i1> %a, <1 x i1> %b) {
; CHECK-LABEL: select_v1i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
-; CHECK-NEXT: vmv.v.x v9, a0
+; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: vmsne.vi v9, v9, 0
; CHECK-NEXT: vmandn.mm v8, v8, v9
; CHECK-NEXT: vmand.mm v9, v0, v9
@@ -24,7 +24,7 @@ define <1 x i1> @selectcc_v1i1(i1 signext %a, i1 signext %b, <1 x i1> %c, <1 x i
; CHECK-NEXT: xor a0, a0, a1
; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
-; CHECK-NEXT: vmv.v.x v9, a0
+; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: vmsne.vi v9, v9, 0
; CHECK-NEXT: vmandn.mm v8, v8, v9
; CHECK-NEXT: vmand.mm v9, v0, v9
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-transpose.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-transpose.ll
index c66a83bdddd551..1bf832a229b218 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-transpose.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-transpose.ll
@@ -11,7 +11,7 @@ define <8 x i8> @trn1.v8i8(<8 x i8> %v0, <8 x i8> %v1) {
; CHECK-NEXT: vid.v v11
; CHECK-NEXT: vrgather.vv v10, v8, v11
; CHECK-NEXT: li a0, 170
-; CHECK-NEXT: vmv.v.x v0, a0
+; CHECK-NEXT: vmv.s.x v0, a0
; CHECK-NEXT: vadd.vi v8, v11, -1
; CHECK-NEXT: vrgather.vv v10, v9, v8, v0.t
; CHECK-NEXT: vmv1r.v v8, v10
@@ -27,7 +27,7 @@ define <8 x i8> @trn2.v8i8(<8 x i8> %v0, <8 x i8> %v1) {
; CHECK-NEXT: vid.v v11
; CHECK-NEXT: vadd.vi v12, v11, 1
; CHECK-NEXT: li a0, 170
-; CHECK-NEXT: vmv.v.x v0, a0
+; CHECK-NEXT: vmv.s.x v0, a0
; CHECK-NEXT: vrgather.vv v10, v8, v12
; CHECK-NEXT: vrgather.vv v10, v9, v11, v0.t
; CHECK-NEXT: vmv1r.v v8, v10
@@ -46,7 +46,7 @@ define <16 x i8> @trn1.v16i8(<16 x i8> %v0, <16 x i8> %v1) {
; RV32-NEXT: lui a0, 11
; RV32-NEXT: addi a0, a0, -1366
; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; RV32-NEXT: vmv.v.x v0, a0
+; RV32-NEXT: vmv.s.x v0, a0
; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; RV32-NEXT: vrgather.vv v10, v9, v8, v0.t
; RV32-NEXT: vmv.v.v v8, v10
@@ -61,7 +61,7 @@ define <16 x i8> @trn1.v16i8(<16 x i8> %v0, <16 x i8> %v1) {
; RV64-NEXT: lui a0, 11
; RV64-NEXT: addiw a0, a0, -1366
; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; RV64-NEXT: vmv.v.x v0, a0
+; RV64-NEXT: vmv.s.x v0, a0
; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; RV64-NEXT: vrgather.vv v10, v9, v8, v0.t
; RV64-NEXT: vmv.v.v v8, v10
@@ -80,7 +80,7 @@ define <16 x i8> @trn2.v16i8(<16 x i8> %v0, <16 x i8> %v1) {
; RV32-NEXT: lui a0, 11
; RV32-NEXT: addi a0, a0, -1366
; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; RV32-NEXT: vmv.v.x v0, a0
+; RV32-NEXT: vmv.s.x v0, a0
; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; RV32-NEXT: vrgather.vv v10, v9, v11, v0.t
; RV32-NEXT: vmv.v.v v8, v10
@@ -95,7 +95,7 @@ define <16 x i8> @trn2.v16i8(<16 x i8> %v0, <16 x i8> %v1) {
; RV64-NEXT: lui a0, 11
; RV64-NEXT: addiw a0, a0, -1366
; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; RV64-NEXT: vmv.v.x v0, a0
+; RV64-NEXT: vmv.s.x v0, a0
; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; RV64-NEXT: vrgather.vv v10, v9, v11, v0.t
; RV64-NEXT: vmv.v.v v8, v10
@@ -141,7 +141,7 @@ define <8 x i16> @trn1.v8i16(<8 x i16> %v0, <8 x i16> %v1) {
; CHECK-NEXT: vid.v v11
; CHECK-NEXT: vrgather.vv v10, v8, v11
; CHECK-NEXT: li a0, 170
-; CHECK-NEXT: vmv.v.x v0, a0
+; CHECK-NEXT: vmv.s.x v0, a0
; CHECK-NEXT: vadd.vi v8, v11, -1
; CHECK-NEXT: vrgather.vv v10, v9, v8, v0.t
; CHECK-NEXT: vmv.v.v v8, v10
@@ -157,7 +157,7 @@ define <8 x i16> @trn2.v8i16(<8 x i16> %v0, <8 x i16> %v1) {
; CHECK-NEXT: vid.v v11
; CHECK-NEXT: vadd.vi v12, v11, 1
; CHECK-NEXT: li a0, 170
-; CHECK-NEXT: vmv.v.x v0, a0
+; CHECK-NEXT: vmv.s.x v0, a0
; CHECK-NEXT: vrgather.vv v10, v8, v12
; CHECK-NEXT: vrgather.vv v10, v9, v11, v0.t
; CHECK-NEXT: vmv.v.v v8, v10
@@ -355,7 +355,7 @@ define <8 x half> @trn1.v8f16(<8 x half> %v0, <8 x half> %v1) {
; CHECK-NEXT: vid.v v11
; CHECK-NEXT: vrgather.vv v10, v8, v11
; CHECK-NEXT: li a0, 170
-; CHECK-NEXT: vmv.v.x v0, a0
+; CHECK-NEXT: vmv.s.x v0, a0
; CHECK-NEXT: vadd.vi v8, v11, -1
; CHECK-NEXT: vrgather.vv v10, v9, v8, v0.t
; CHECK-NEXT: vmv.v.v v8, v10
@@ -371,7 +371,7 @@ define <8 x half> @trn2.v8f16(<8 x half> %v0, <8 x half> %v1) {
; CHECK-NEXT: vid.v v11
; CHECK-NEXT: vadd.vi v12, v11, 1
; CHECK-NEXT: li a0, 170
-; CHECK-NEXT: vmv.v.x v0, a0
+; CHECK-NEXT: vmv.s.x v0, a0
; CHECK-NEXT: vrgather.vv v10, v8, v12
; CHECK-NEXT: vrgather.vv v10, v9, v11, v0.t
; CHECK-NEXT: vmv.v.v v8, v10
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store-asm.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store-asm.ll
index bd59f28dd4eba9..311491fa6018c9 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store-asm.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store-asm.ll
@@ -58,7 +58,7 @@ define void @gather_masked(ptr noalias nocapture %A, ptr noalias nocapture reado
; V-NEXT: lui a3, 983765
; V-NEXT: addiw a3, a3, 873
; V-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; V-NEXT: vmv.v.x v0, a3
+; V-NEXT: vmv.s.x v0, a3
; V-NEXT: li a3, 32
; V-NEXT: li a4, 5
; V-NEXT: .LBB1_1: # %vector.body
@@ -82,7 +82,7 @@ define void @gather_masked(ptr noalias nocapture %A, ptr noalias nocapture reado
; ZVE32F-NEXT: lui a3, 983765
; ZVE32F-NEXT: addiw a3, a3, 873
; ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; ZVE32F-NEXT: vmv.v.x v0, a3
+; ZVE32F-NEXT: vmv.s.x v0, a3
; ZVE32F-NEXT: li a3, 32
; ZVE32F-NEXT: li a4, 5
; ZVE32F-NEXT: .LBB1_1: # %vector.body
@@ -333,7 +333,7 @@ define void @scatter_masked(ptr noalias nocapture %A, ptr noalias nocapture read
; V-NEXT: lui a4, 983765
; V-NEXT: addiw a4, a4, 873
; V-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; V-NEXT: vmv.v.x v0, a4
+; V-NEXT: vmv.s.x v0, a4
; V-NEXT: li a4, 5
; V-NEXT: .LBB6_1: # %vector.body
; V-NEXT: # =>This Inner Loop Header: Depth=1
@@ -357,7 +357,7 @@ define void @scatter_masked(ptr noalias nocapture %A, ptr noalias nocapture read
; ZVE32F-NEXT: lui a4, 983765
; ZVE32F-NEXT: addiw a4, a4, 873
; ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; ZVE32F-NEXT: vmv.v.x v0, a4
+; ZVE32F-NEXT: vmv.s.x v0, a4
; ZVE32F-NEXT: li a4, 5
; ZVE32F-NEXT: .LBB6_1: # %vector.body
; ZVE32F-NEXT: # =>This Inner Loop Header: Depth=1
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll
index ad6aeb0f700139..df8754cdb23400 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll
@@ -1296,12 +1296,10 @@ define <11 x i64> @vand_vx_v11i64(<11 x i64> %va, i64 %b, <11 x i1> %m, i32 zero
; RV32-NEXT: vmv1r.v v16, v0
; RV32-NEXT: li a3, 32
; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma
+; RV32-NEXT: lui a3, 341
+; RV32-NEXT: addi a3, a3, 1365
+; RV32-NEXT: vmv.s.x v0, a3
; RV32-NEXT: vmv.v.x v24, a1
-; RV32-NEXT: lui a1, 341
-; RV32-NEXT: addi a1, a1, 1365
-; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; RV32-NEXT: vmv.v.x v0, a1
-; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; RV32-NEXT: vmerge.vxm v24, v24, a0, v0
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vmv1r.v v0, v16
@@ -1324,12 +1322,10 @@ define <11 x i64> @vand_vx_v11i64_unmasked(<11 x i64> %va, i64 %b, i32 zeroext %
; RV32: # %bb.0:
; RV32-NEXT: li a3, 32
; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma
+; RV32-NEXT: lui a3, 341
+; RV32-NEXT: addi a3, a3, 1365
+; RV32-NEXT: vmv.s.x v0, a3
; RV32-NEXT: vmv.v.x v16, a1
-; RV32-NEXT: lui a1, 341
-; RV32-NEXT: addi a1, a1, 1365
-; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; RV32-NEXT: vmv.v.x v0, a1
-; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; RV32-NEXT: vmerge.vxm v16, v16, a0, v0
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vand.vv v8, v8, v16
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfcmp-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfcmp-constrained-sdnode.ll
index afd07bebf072cc..a8b6e671c644fe 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfcmp-constrained-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfcmp-constrained-sdnode.ll
@@ -56,7 +56,7 @@ define <1 x i1> @fcmp_ogt_vf_v1f16(<1 x half> %va, half %b) nounwind strictfp {
; CHECK-LABEL: fcmp_ogt_vf_v1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
@@ -72,7 +72,7 @@ define <1 x i1> @fcmp_ogt_fv_v1f16(<1 x half> %va, half %b) nounwind strictfp {
; CHECK-LABEL: fcmp_ogt_fv_v1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
@@ -101,7 +101,7 @@ define <1 x i1> @fcmp_oge_vf_v1f16(<1 x half> %va, half %b) nounwind strictfp {
; CHECK-LABEL: fcmp_oge_vf_v1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
@@ -117,7 +117,7 @@ define <1 x i1> @fcmp_oge_fv_v1f16(<1 x half> %va, half %b) nounwind strictfp {
; CHECK-LABEL: fcmp_oge_fv_v1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
@@ -146,7 +146,7 @@ define <1 x i1> @fcmp_olt_vf_v1f16(<1 x half> %va, half %b) nounwind strictfp {
; CHECK-LABEL: fcmp_olt_vf_v1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
@@ -162,7 +162,7 @@ define <1 x i1> @fcmp_olt_fv_v1f16(<1 x half> %va, half %b) nounwind strictfp {
; CHECK-LABEL: fcmp_olt_fv_v1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
@@ -191,7 +191,7 @@ define <1 x i1> @fcmp_ole_vf_v1f16(<1 x half> %va, half %b) nounwind strictfp {
; CHECK-LABEL: fcmp_ole_vf_v1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
@@ -207,7 +207,7 @@ define <1 x i1> @fcmp_ole_fv_v1f16(<1 x half> %va, half %b) nounwind strictfp {
; CHECK-LABEL: fcmp_ole_fv_v1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
@@ -239,7 +239,7 @@ define <1 x i1> @fcmp_one_vf_v1f16(<1 x half> %va, half %b) nounwind strictfp {
; CHECK-LABEL: fcmp_one_vf_v1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
@@ -258,7 +258,7 @@ define <1 x i1> @fcmp_one_fv_v1f16(<1 x half> %va, half %b) nounwind strictfp {
; CHECK-LABEL: fcmp_one_fv_v1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
@@ -289,7 +289,7 @@ define <1 x i1> @fcmp_ord_vf_v1f16(<1 x half> %va, half %b) nounwind strictfp {
; CHECK-LABEL: fcmp_ord_vf_v1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
; CHECK-NEXT: vmfeq.vv v8, v8, v8
; CHECK-NEXT: vmand.mm v0, v8, v9
@@ -304,7 +304,7 @@ define <1 x i1> @fcmp_ord_fv_v1f16(<1 x half> %va, half %b) nounwind strictfp {
; CHECK-LABEL: fcmp_ord_fv_v1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
; CHECK-NEXT: vmfeq.vv v8, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v8
@@ -335,7 +335,7 @@ define <1 x i1> @fcmp_ueq_vf_v1f16(<1 x half> %va, half %b) nounwind strictfp {
; CHECK-LABEL: fcmp_ueq_vf_v1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
@@ -354,7 +354,7 @@ define <1 x i1> @fcmp_ueq_fv_v1f16(<1 x half> %va, half %b) nounwind strictfp {
; CHECK-LABEL: fcmp_ueq_fv_v1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
@@ -387,7 +387,7 @@ define <1 x i1> @fcmp_ugt_vf_v1f16(<1 x half> %va, half %b) nounwind strictfp {
; CHECK-LABEL: fcmp_ugt_vf_v1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
@@ -404,7 +404,7 @@ define <1 x i1> @fcmp_ugt_fv_v1f16(<1 x half> %va, half %b) nounwind strictfp {
; CHECK-LABEL: fcmp_ugt_fv_v1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
@@ -435,7 +435,7 @@ define <1 x i1> @fcmp_uge_vf_v1f16(<1 x half> %va, half %b) nounwind strictfp {
; CHECK-LABEL: fcmp_uge_vf_v1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
@@ -452,7 +452,7 @@ define <1 x i1> @fcmp_uge_fv_v1f16(<1 x half> %va, half %b) nounwind strictfp {
; CHECK-LABEL: fcmp_uge_fv_v1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
@@ -483,7 +483,7 @@ define <1 x i1> @fcmp_ult_vf_v1f16(<1 x half> %va, half %b) nounwind strictfp {
; CHECK-LABEL: fcmp_ult_vf_v1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
@@ -500,7 +500,7 @@ define <1 x i1> @fcmp_ult_fv_v1f16(<1 x half> %va, half %b) nounwind strictfp {
; CHECK-LABEL: fcmp_ult_fv_v1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
@@ -531,7 +531,7 @@ define <1 x i1> @fcmp_ule_vf_v1f16(<1 x half> %va, half %b) nounwind strictfp {
; CHECK-LABEL: fcmp_ule_vf_v1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
@@ -548,7 +548,7 @@ define <1 x i1> @fcmp_ule_fv_v1f16(<1 x half> %va, half %b) nounwind strictfp {
; CHECK-LABEL: fcmp_ule_fv_v1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
@@ -611,7 +611,7 @@ define <1 x i1> @fcmp_uno_vf_v1f16(<1 x half> %va, half %b) nounwind strictfp {
; CHECK-LABEL: fcmp_uno_vf_v1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfne.vf v9, v9, fa0
; CHECK-NEXT: vmfne.vv v8, v8, v8
; CHECK-NEXT: vmor.mm v0, v8, v9
@@ -626,7 +626,7 @@ define <1 x i1> @fcmp_uno_fv_v1f16(<1 x half> %va, half %b) nounwind strictfp {
; CHECK-LABEL: fcmp_uno_fv_v1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfne.vf v9, v9, fa0
; CHECK-NEXT: vmfne.vv v8, v8, v8
; CHECK-NEXT: vmor.mm v0, v9, v8
@@ -3980,7 +3980,7 @@ define <1 x i1> @fcmp_ogt_vf_v1f32(<1 x float> %va, float %b) nounwind strictfp
; CHECK-LABEL: fcmp_ogt_vf_v1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
@@ -3996,7 +3996,7 @@ define <1 x i1> @fcmp_ogt_fv_v1f32(<1 x float> %va, float %b) nounwind strictfp
; CHECK-LABEL: fcmp_ogt_fv_v1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
@@ -4025,7 +4025,7 @@ define <1 x i1> @fcmp_oge_vf_v1f32(<1 x float> %va, float %b) nounwind strictfp
; CHECK-LABEL: fcmp_oge_vf_v1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
@@ -4041,7 +4041,7 @@ define <1 x i1> @fcmp_oge_fv_v1f32(<1 x float> %va, float %b) nounwind strictfp
; CHECK-LABEL: fcmp_oge_fv_v1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
@@ -4070,7 +4070,7 @@ define <1 x i1> @fcmp_olt_vf_v1f32(<1 x float> %va, float %b) nounwind strictfp
; CHECK-LABEL: fcmp_olt_vf_v1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
@@ -4086,7 +4086,7 @@ define <1 x i1> @fcmp_olt_fv_v1f32(<1 x float> %va, float %b) nounwind strictfp
; CHECK-LABEL: fcmp_olt_fv_v1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
@@ -4115,7 +4115,7 @@ define <1 x i1> @fcmp_ole_vf_v1f32(<1 x float> %va, float %b) nounwind strictfp
; CHECK-LABEL: fcmp_ole_vf_v1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
@@ -4131,7 +4131,7 @@ define <1 x i1> @fcmp_ole_fv_v1f32(<1 x float> %va, float %b) nounwind strictfp
; CHECK-LABEL: fcmp_ole_fv_v1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
@@ -4163,7 +4163,7 @@ define <1 x i1> @fcmp_one_vf_v1f32(<1 x float> %va, float %b) nounwind strictfp
; CHECK-LABEL: fcmp_one_vf_v1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
@@ -4182,7 +4182,7 @@ define <1 x i1> @fcmp_one_fv_v1f32(<1 x float> %va, float %b) nounwind strictfp
; CHECK-LABEL: fcmp_one_fv_v1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
@@ -4213,7 +4213,7 @@ define <1 x i1> @fcmp_ord_vf_v1f32(<1 x float> %va, float %b) nounwind strictfp
; CHECK-LABEL: fcmp_ord_vf_v1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
; CHECK-NEXT: vmfeq.vv v8, v8, v8
; CHECK-NEXT: vmand.mm v0, v8, v9
@@ -4228,7 +4228,7 @@ define <1 x i1> @fcmp_ord_fv_v1f32(<1 x float> %va, float %b) nounwind strictfp
; CHECK-LABEL: fcmp_ord_fv_v1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
; CHECK-NEXT: vmfeq.vv v8, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v8
@@ -4259,7 +4259,7 @@ define <1 x i1> @fcmp_ueq_vf_v1f32(<1 x float> %va, float %b) nounwind strictfp
; CHECK-LABEL: fcmp_ueq_vf_v1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
@@ -4278,7 +4278,7 @@ define <1 x i1> @fcmp_ueq_fv_v1f32(<1 x float> %va, float %b) nounwind strictfp
; CHECK-LABEL: fcmp_ueq_fv_v1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
@@ -4311,7 +4311,7 @@ define <1 x i1> @fcmp_ugt_vf_v1f32(<1 x float> %va, float %b) nounwind strictfp
; CHECK-LABEL: fcmp_ugt_vf_v1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
@@ -4328,7 +4328,7 @@ define <1 x i1> @fcmp_ugt_fv_v1f32(<1 x float> %va, float %b) nounwind strictfp
; CHECK-LABEL: fcmp_ugt_fv_v1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
@@ -4359,7 +4359,7 @@ define <1 x i1> @fcmp_uge_vf_v1f32(<1 x float> %va, float %b) nounwind strictfp
; CHECK-LABEL: fcmp_uge_vf_v1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
@@ -4376,7 +4376,7 @@ define <1 x i1> @fcmp_uge_fv_v1f32(<1 x float> %va, float %b) nounwind strictfp
; CHECK-LABEL: fcmp_uge_fv_v1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
@@ -4407,7 +4407,7 @@ define <1 x i1> @fcmp_ult_vf_v1f32(<1 x float> %va, float %b) nounwind strictfp
; CHECK-LABEL: fcmp_ult_vf_v1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
@@ -4424,7 +4424,7 @@ define <1 x i1> @fcmp_ult_fv_v1f32(<1 x float> %va, float %b) nounwind strictfp
; CHECK-LABEL: fcmp_ult_fv_v1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
@@ -4455,7 +4455,7 @@ define <1 x i1> @fcmp_ule_vf_v1f32(<1 x float> %va, float %b) nounwind strictfp
; CHECK-LABEL: fcmp_ule_vf_v1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
@@ -4472,7 +4472,7 @@ define <1 x i1> @fcmp_ule_fv_v1f32(<1 x float> %va, float %b) nounwind strictfp
; CHECK-LABEL: fcmp_ule_fv_v1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
@@ -4535,7 +4535,7 @@ define <1 x i1> @fcmp_uno_vf_v1f32(<1 x float> %va, float %b) nounwind strictfp
; CHECK-LABEL: fcmp_uno_vf_v1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfne.vf v9, v9, fa0
; CHECK-NEXT: vmfne.vv v8, v8, v8
; CHECK-NEXT: vmor.mm v0, v8, v9
@@ -4550,7 +4550,7 @@ define <1 x i1> @fcmp_uno_fv_v1f32(<1 x float> %va, float %b) nounwind strictfp
; CHECK-LABEL: fcmp_uno_fv_v1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfne.vf v9, v9, fa0
; CHECK-NEXT: vmfne.vv v8, v8, v8
; CHECK-NEXT: vmor.mm v0, v9, v8
@@ -7229,7 +7229,7 @@ define <1 x i1> @fcmp_ogt_vf_v1f64(<1 x double> %va, double %b) nounwind strictf
; CHECK-LABEL: fcmp_ogt_vf_v1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
@@ -7245,7 +7245,7 @@ define <1 x i1> @fcmp_ogt_fv_v1f64(<1 x double> %va, double %b) nounwind strictf
; CHECK-LABEL: fcmp_ogt_fv_v1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
@@ -7274,7 +7274,7 @@ define <1 x i1> @fcmp_oge_vf_v1f64(<1 x double> %va, double %b) nounwind strictf
; CHECK-LABEL: fcmp_oge_vf_v1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
@@ -7290,7 +7290,7 @@ define <1 x i1> @fcmp_oge_fv_v1f64(<1 x double> %va, double %b) nounwind strictf
; CHECK-LABEL: fcmp_oge_fv_v1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
@@ -7319,7 +7319,7 @@ define <1 x i1> @fcmp_olt_vf_v1f64(<1 x double> %va, double %b) nounwind strictf
; CHECK-LABEL: fcmp_olt_vf_v1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
@@ -7335,7 +7335,7 @@ define <1 x i1> @fcmp_olt_fv_v1f64(<1 x double> %va, double %b) nounwind strictf
; CHECK-LABEL: fcmp_olt_fv_v1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
@@ -7364,7 +7364,7 @@ define <1 x i1> @fcmp_ole_vf_v1f64(<1 x double> %va, double %b) nounwind strictf
; CHECK-LABEL: fcmp_ole_vf_v1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
@@ -7380,7 +7380,7 @@ define <1 x i1> @fcmp_ole_fv_v1f64(<1 x double> %va, double %b) nounwind strictf
; CHECK-LABEL: fcmp_ole_fv_v1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
@@ -7412,7 +7412,7 @@ define <1 x i1> @fcmp_one_vf_v1f64(<1 x double> %va, double %b) nounwind strictf
; CHECK-LABEL: fcmp_one_vf_v1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
@@ -7431,7 +7431,7 @@ define <1 x i1> @fcmp_one_fv_v1f64(<1 x double> %va, double %b) nounwind strictf
; CHECK-LABEL: fcmp_one_fv_v1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
@@ -7462,7 +7462,7 @@ define <1 x i1> @fcmp_ord_vf_v1f64(<1 x double> %va, double %b) nounwind strictf
; CHECK-LABEL: fcmp_ord_vf_v1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
; CHECK-NEXT: vmfeq.vv v8, v8, v8
; CHECK-NEXT: vmand.mm v0, v8, v9
@@ -7477,7 +7477,7 @@ define <1 x i1> @fcmp_ord_fv_v1f64(<1 x double> %va, double %b) nounwind strictf
; CHECK-LABEL: fcmp_ord_fv_v1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
; CHECK-NEXT: vmfeq.vv v8, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v8
@@ -7508,7 +7508,7 @@ define <1 x i1> @fcmp_ueq_vf_v1f64(<1 x double> %va, double %b) nounwind strictf
; CHECK-LABEL: fcmp_ueq_vf_v1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
@@ -7527,7 +7527,7 @@ define <1 x i1> @fcmp_ueq_fv_v1f64(<1 x double> %va, double %b) nounwind strictf
; CHECK-LABEL: fcmp_ueq_fv_v1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
@@ -7560,7 +7560,7 @@ define <1 x i1> @fcmp_ugt_vf_v1f64(<1 x double> %va, double %b) nounwind strictf
; CHECK-LABEL: fcmp_ugt_vf_v1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
@@ -7577,7 +7577,7 @@ define <1 x i1> @fcmp_ugt_fv_v1f64(<1 x double> %va, double %b) nounwind strictf
; CHECK-LABEL: fcmp_ugt_fv_v1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
@@ -7608,7 +7608,7 @@ define <1 x i1> @fcmp_uge_vf_v1f64(<1 x double> %va, double %b) nounwind strictf
; CHECK-LABEL: fcmp_uge_vf_v1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
@@ -7625,7 +7625,7 @@ define <1 x i1> @fcmp_uge_fv_v1f64(<1 x double> %va, double %b) nounwind strictf
; CHECK-LABEL: fcmp_uge_fv_v1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
@@ -7656,7 +7656,7 @@ define <1 x i1> @fcmp_ult_vf_v1f64(<1 x double> %va, double %b) nounwind strictf
; CHECK-LABEL: fcmp_ult_vf_v1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
@@ -7673,7 +7673,7 @@ define <1 x i1> @fcmp_ult_fv_v1f64(<1 x double> %va, double %b) nounwind strictf
; CHECK-LABEL: fcmp_ult_fv_v1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
@@ -7704,7 +7704,7 @@ define <1 x i1> @fcmp_ule_vf_v1f64(<1 x double> %va, double %b) nounwind strictf
; CHECK-LABEL: fcmp_ule_vf_v1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
@@ -7721,7 +7721,7 @@ define <1 x i1> @fcmp_ule_fv_v1f64(<1 x double> %va, double %b) nounwind strictf
; CHECK-LABEL: fcmp_ule_fv_v1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
@@ -7784,7 +7784,7 @@ define <1 x i1> @fcmp_uno_vf_v1f64(<1 x double> %va, double %b) nounwind strictf
; CHECK-LABEL: fcmp_uno_vf_v1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfne.vf v9, v9, fa0
; CHECK-NEXT: vmfne.vv v8, v8, v8
; CHECK-NEXT: vmor.mm v0, v8, v9
@@ -7799,7 +7799,7 @@ define <1 x i1> @fcmp_uno_fv_v1f64(<1 x double> %va, double %b) nounwind strictf
; CHECK-LABEL: fcmp_uno_fv_v1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfne.vf v9, v9, fa0
; CHECK-NEXT: vmfne.vv v8, v8, v8
; CHECK-NEXT: vmor.mm v0, v9, v8
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfcmps-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfcmps-constrained-sdnode.ll
index 8243e86c744701..9a3d68d7e5d24f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfcmps-constrained-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfcmps-constrained-sdnode.ll
@@ -237,7 +237,7 @@ define <1 x i1> @fcmps_ord_vf_v1f16(<1 x half> %va, half %b) nounwind strictfp {
; CHECK-LABEL: fcmps_ord_vf_v1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfle.vf v9, v9, fa0
; CHECK-NEXT: vmfle.vv v8, v8, v8
; CHECK-NEXT: vmand.mm v0, v8, v9
@@ -252,7 +252,7 @@ define <1 x i1> @fcmps_ord_fv_v1f16(<1 x half> %va, half %b) nounwind strictfp {
; CHECK-LABEL: fcmps_ord_fv_v1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfle.vf v9, v9, fa0
; CHECK-NEXT: vmfle.vv v8, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v8
@@ -508,7 +508,7 @@ define <1 x i1> @fcmps_uno_vf_v1f16(<1 x half> %va, half %b) nounwind strictfp {
; CHECK-LABEL: fcmps_uno_vf_v1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfle.vf v9, v9, fa0
; CHECK-NEXT: vmfle.vv v8, v8, v8
; CHECK-NEXT: vmnot.m v8, v8
@@ -524,7 +524,7 @@ define <1 x i1> @fcmps_uno_fv_v1f16(<1 x half> %va, half %b) nounwind strictfp {
; CHECK-LABEL: fcmps_uno_fv_v1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfle.vf v9, v9, fa0
; CHECK-NEXT: vmnot.m v9, v9
; CHECK-NEXT: vmfle.vv v8, v8, v8
@@ -3471,7 +3471,7 @@ define <1 x i1> @fcmps_ord_vf_v1f32(<1 x float> %va, float %b) nounwind strictfp
; CHECK-LABEL: fcmps_ord_vf_v1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfle.vf v9, v9, fa0
; CHECK-NEXT: vmfle.vv v8, v8, v8
; CHECK-NEXT: vmand.mm v0, v8, v9
@@ -3486,7 +3486,7 @@ define <1 x i1> @fcmps_ord_fv_v1f32(<1 x float> %va, float %b) nounwind strictfp
; CHECK-LABEL: fcmps_ord_fv_v1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfle.vf v9, v9, fa0
; CHECK-NEXT: vmfle.vv v8, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v8
@@ -3742,7 +3742,7 @@ define <1 x i1> @fcmps_uno_vf_v1f32(<1 x float> %va, float %b) nounwind strictfp
; CHECK-LABEL: fcmps_uno_vf_v1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfle.vf v9, v9, fa0
; CHECK-NEXT: vmfle.vv v8, v8, v8
; CHECK-NEXT: vmnot.m v8, v8
@@ -3758,7 +3758,7 @@ define <1 x i1> @fcmps_uno_fv_v1f32(<1 x float> %va, float %b) nounwind strictfp
; CHECK-LABEL: fcmps_uno_fv_v1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfle.vf v9, v9, fa0
; CHECK-NEXT: vmnot.m v9, v9
; CHECK-NEXT: vmfle.vv v8, v8, v8
@@ -6131,7 +6131,7 @@ define <1 x i1> @fcmps_ord_vf_v1f64(<1 x double> %va, double %b) nounwind strict
; CHECK-LABEL: fcmps_ord_vf_v1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfle.vf v9, v9, fa0
; CHECK-NEXT: vmfle.vv v8, v8, v8
; CHECK-NEXT: vmand.mm v0, v8, v9
@@ -6146,7 +6146,7 @@ define <1 x i1> @fcmps_ord_fv_v1f64(<1 x double> %va, double %b) nounwind strict
; CHECK-LABEL: fcmps_ord_fv_v1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfle.vf v9, v9, fa0
; CHECK-NEXT: vmfle.vv v8, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v8
@@ -6402,7 +6402,7 @@ define <1 x i1> @fcmps_uno_vf_v1f64(<1 x double> %va, double %b) nounwind strict
; CHECK-LABEL: fcmps_uno_vf_v1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfle.vf v9, v9, fa0
; CHECK-NEXT: vmfle.vv v8, v8, v8
; CHECK-NEXT: vmnot.m v8, v8
@@ -6418,7 +6418,7 @@ define <1 x i1> @fcmps_uno_fv_v1f64(<1 x double> %va, double %b) nounwind strict
; CHECK-LABEL: fcmps_uno_fv_v1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
-; CHECK-NEXT: vfmv.v.f v9, fa0
+; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmfle.vf v9, v9, fa0
; CHECK-NEXT: vmnot.m v9, v9
; CHECK-NEXT: vmfle.vv v8, v8, v8
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmacc.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmacc.ll
index cae6f591968a82..167840c1a0d1c6 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmacc.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmacc.ll
@@ -1330,7 +1330,7 @@ define <1 x double> @vfwmacc_vf_v1f64_v1f16(<1 x double> %va, <1 x half> %vb, ha
; CHECK-LABEL: vfwmacc_vf_v1f64_v1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; CHECK-NEXT: vfmv.v.f v10, fa0
+; CHECK-NEXT: vfmv.s.f v10, fa0
; CHECK-NEXT: vfwcvt.f.f.v v11, v9
; CHECK-NEXT: vfwcvt.f.f.v v9, v10
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
@@ -1365,7 +1365,7 @@ define <1 x double> @vfwnmacc_vf_v1f64_v1f16(<1 x double> %va, <1 x half> %vb, h
; CHECK-LABEL: vfwnmacc_vf_v1f64_v1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; CHECK-NEXT: vfmv.v.f v10, fa0
+; CHECK-NEXT: vfmv.s.f v10, fa0
; CHECK-NEXT: vfwcvt.f.f.v v11, v9
; CHECK-NEXT: vfwcvt.f.f.v v9, v10
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
@@ -1385,7 +1385,7 @@ define <1 x double> @vfwnmacc_fv_v1f64_v1f16(<1 x double> %va, <1 x half> %vb, h
; CHECK-LABEL: vfwnmacc_fv_v1f64_v1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; CHECK-NEXT: vfmv.v.f v10, fa0
+; CHECK-NEXT: vfmv.s.f v10, fa0
; CHECK-NEXT: vfwcvt.f.f.v v11, v9
; CHECK-NEXT: vfwcvt.f.f.v v9, v10
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
@@ -1421,7 +1421,7 @@ define <1 x double> @vfwmsac_vf_v1f64_v1f16(<1 x double> %va, <1 x half> %vb, ha
; CHECK-LABEL: vfwmsac_vf_v1f64_v1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; CHECK-NEXT: vfmv.v.f v10, fa0
+; CHECK-NEXT: vfmv.s.f v10, fa0
; CHECK-NEXT: vfwcvt.f.f.v v11, v9
; CHECK-NEXT: vfwcvt.f.f.v v9, v10
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
@@ -1456,7 +1456,7 @@ define <1 x double> @vfwnmsac_vf_v1f64_v1f16(<1 x double> %va, <1 x half> %vb, h
; CHECK-LABEL: vfwnmsac_vf_v1f64_v1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; CHECK-NEXT: vfmv.v.f v10, fa0
+; CHECK-NEXT: vfmv.s.f v10, fa0
; CHECK-NEXT: vfwcvt.f.f.v v11, v9
; CHECK-NEXT: vfwcvt.f.f.v v9, v10
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
@@ -1475,7 +1475,7 @@ define <1 x double> @vfwnmsac_fv_v1f64_v1f16(<1 x double> %va, <1 x half> %vb, h
; CHECK-LABEL: vfwnmsac_fv_v1f64_v1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; CHECK-NEXT: vfmv.v.f v10, fa0
+; CHECK-NEXT: vfmv.s.f v10, fa0
; CHECK-NEXT: vfwcvt.f.f.v v11, v9
; CHECK-NEXT: vfwcvt.f.f.v v9, v10
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vitofp-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vitofp-constrained-sdnode.ll
index a1e839091ca3d7..b19c30df55114e 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vitofp-constrained-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vitofp-constrained-sdnode.ll
@@ -9,7 +9,7 @@ define <1 x half> @vsitofp_v1i1_v1f16(<1 x i1> %va) strictfp {
; CHECK-LABEL: vsitofp_v1i1_v1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
-; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmv.s.x v8, zero
; CHECK-NEXT: vmerge.vim v9, v8, -1, v0
; CHECK-NEXT: vfwcvt.f.x.v v8, v9
; CHECK-NEXT: ret
@@ -22,7 +22,7 @@ define <1 x half> @vuitofp_v1i1_v1f16(<1 x i1> %va) strictfp {
; CHECK-LABEL: vuitofp_v1i1_v1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
-; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmv.s.x v8, zero
; CHECK-NEXT: vmerge.vim v9, v8, 1, v0
; CHECK-NEXT: vfwcvt.f.xu.v v8, v9
; CHECK-NEXT: ret
@@ -35,7 +35,7 @@ define <1 x float> @vsitofp_v1i1_v1f32(<1 x i1> %va) strictfp {
; CHECK-LABEL: vsitofp_v1i1_v1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmv.s.x v8, zero
; CHECK-NEXT: vmerge.vim v9, v8, -1, v0
; CHECK-NEXT: vfwcvt.f.x.v v8, v9
; CHECK-NEXT: ret
@@ -48,7 +48,7 @@ define <1 x float> @vuitofp_v1i1_v1f32(<1 x i1> %va) strictfp {
; CHECK-LABEL: vuitofp_v1i1_v1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmv.s.x v8, zero
; CHECK-NEXT: vmerge.vim v9, v8, 1, v0
; CHECK-NEXT: vfwcvt.f.xu.v v8, v9
; CHECK-NEXT: ret
@@ -61,7 +61,7 @@ define <1 x double> @vsitofp_v1i1_v1f64(<1 x i1> %va) strictfp {
; CHECK-LABEL: vsitofp_v1i1_v1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmv.s.x v8, zero
; CHECK-NEXT: vmerge.vim v9, v8, -1, v0
; CHECK-NEXT: vfwcvt.f.x.v v8, v9
; CHECK-NEXT: ret
@@ -74,7 +74,7 @@ define <1 x double> @vuitofp_v1i1_v1f64(<1 x i1> %va) strictfp {
; CHECK-LABEL: vuitofp_v1i1_v1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmv.s.x v8, zero
; CHECK-NEXT: vmerge.vim v9, v8, 1, v0
; CHECK-NEXT: vfwcvt.f.xu.v v8, v9
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrol.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrol.ll
index 82c160577a50ed..a2516ce9f7d46a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrol.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrol.ll
@@ -31,7 +31,7 @@ define <1 x i8> @vrol_vx_v1i8(<1 x i8> %a, i8 %b) {
; CHECK-LABEL: vrol_vx_v1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
-; CHECK-NEXT: vmv.v.x v9, a0
+; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: vand.vi v10, v9, 7
; CHECK-NEXT: vsll.vv v10, v8, v10
; CHECK-NEXT: vrsub.vi v9, v9, 0
@@ -368,7 +368,7 @@ define <1 x i16> @vrol_vx_v1i16(<1 x i16> %a, i16 %b) {
; CHECK-LABEL: vrol_vx_v1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; CHECK-NEXT: vmv.v.x v9, a0
+; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: vand.vi v10, v9, 15
; CHECK-NEXT: vsll.vv v10, v8, v10
; CHECK-NEXT: vrsub.vi v9, v9, 0
@@ -655,7 +655,7 @@ define <1 x i32> @vrol_vx_v1i32(<1 x i32> %a, i32 %b) {
; CHECK-LABEL: vrol_vx_v1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; CHECK-NEXT: vmv.v.x v9, a0
+; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: li a0, 31
; CHECK-NEXT: vand.vx v10, v9, a0
; CHECK-NEXT: vsll.vv v10, v8, v10
@@ -897,18 +897,31 @@ define <1 x i64> @vrol_vv_v1i64(<1 x i64> %a, <1 x i64> %b) {
}
define <1 x i64> @vrol_vx_v1i64(<1 x i64> %a, i64 %b) {
-; CHECK-LABEL: vrol_vx_v1i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
-; CHECK-NEXT: vmv.v.x v9, a0
-; CHECK-NEXT: li a0, 63
-; CHECK-NEXT: vand.vx v10, v9, a0
-; CHECK-NEXT: vsll.vv v10, v8, v10
-; CHECK-NEXT: vrsub.vi v9, v9, 0
-; CHECK-NEXT: vand.vx v9, v9, a0
-; CHECK-NEXT: vsrl.vv v8, v8, v9
-; CHECK-NEXT: vor.vv v8, v10, v8
-; CHECK-NEXT: ret
+; CHECK-RV32-LABEL: vrol_vx_v1i64:
+; CHECK-RV32: # %bb.0:
+; CHECK-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; CHECK-RV32-NEXT: vmv.v.x v9, a0
+; CHECK-RV32-NEXT: li a0, 63
+; CHECK-RV32-NEXT: vand.vx v10, v9, a0
+; CHECK-RV32-NEXT: vsll.vv v10, v8, v10
+; CHECK-RV32-NEXT: vrsub.vi v9, v9, 0
+; CHECK-RV32-NEXT: vand.vx v9, v9, a0
+; CHECK-RV32-NEXT: vsrl.vv v8, v8, v9
+; CHECK-RV32-NEXT: vor.vv v8, v10, v8
+; CHECK-RV32-NEXT: ret
+;
+; CHECK-RV64-LABEL: vrol_vx_v1i64:
+; CHECK-RV64: # %bb.0:
+; CHECK-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; CHECK-RV64-NEXT: vmv.s.x v9, a0
+; CHECK-RV64-NEXT: li a0, 63
+; CHECK-RV64-NEXT: vand.vx v10, v9, a0
+; CHECK-RV64-NEXT: vsll.vv v10, v8, v10
+; CHECK-RV64-NEXT: vrsub.vi v9, v9, 0
+; CHECK-RV64-NEXT: vand.vx v9, v9, a0
+; CHECK-RV64-NEXT: vsrl.vv v8, v8, v9
+; CHECK-RV64-NEXT: vor.vv v8, v10, v8
+; CHECK-RV64-NEXT: ret
;
; CHECK-ZVBB-LABEL: vrol_vx_v1i64:
; CHECK-ZVBB: # %bb.0:
@@ -1069,7 +1082,5 @@ define <8 x i64> @vrol_vx_v8i64(<8 x i64> %a, i64 %b) {
}
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; CHECK-RV32: {{.*}}
-; CHECK-RV64: {{.*}}
; CHECK-ZVBB32: {{.*}}
; CHECK-ZVBB64: {{.*}}
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vror.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vror.ll
index 4f26ef8fd491fe..46af856a32b244 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vror.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vror.ll
@@ -32,7 +32,7 @@ define <1 x i8> @vror_vx_v1i8(<1 x i8> %a, i8 %b) {
; CHECK-LABEL: vror_vx_v1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
-; CHECK-NEXT: vmv.v.x v9, a0
+; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: vand.vi v10, v9, 7
; CHECK-NEXT: vsrl.vv v10, v8, v10
; CHECK-NEXT: vrsub.vi v9, v9, 0
@@ -636,7 +636,7 @@ define <1 x i16> @vror_vx_v1i16(<1 x i16> %a, i16 %b) {
; CHECK-LABEL: vror_vx_v1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; CHECK-NEXT: vmv.v.x v9, a0
+; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: vand.vi v10, v9, 15
; CHECK-NEXT: vsrl.vv v10, v8, v10
; CHECK-NEXT: vrsub.vi v9, v9, 0
@@ -1149,7 +1149,7 @@ define <1 x i32> @vror_vx_v1i32(<1 x i32> %a, i32 %b) {
; CHECK-LABEL: vror_vx_v1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; CHECK-NEXT: vmv.v.x v9, a0
+; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: li a0, 31
; CHECK-NEXT: vand.vx v10, v9, a0
; CHECK-NEXT: vsrl.vv v10, v8, v10
@@ -1576,18 +1576,31 @@ define <1 x i64> @vror_vv_v1i64(<1 x i64> %a, <1 x i64> %b) {
}
define <1 x i64> @vror_vx_v1i64(<1 x i64> %a, i64 %b) {
-; CHECK-LABEL: vror_vx_v1i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
-; CHECK-NEXT: vmv.v.x v9, a0
-; CHECK-NEXT: li a0, 63
-; CHECK-NEXT: vand.vx v10, v9, a0
-; CHECK-NEXT: vsrl.vv v10, v8, v10
-; CHECK-NEXT: vrsub.vi v9, v9, 0
-; CHECK-NEXT: vand.vx v9, v9, a0
-; CHECK-NEXT: vsll.vv v8, v8, v9
-; CHECK-NEXT: vor.vv v8, v10, v8
-; CHECK-NEXT: ret
+; CHECK-RV32-LABEL: vror_vx_v1i64:
+; CHECK-RV32: # %bb.0:
+; CHECK-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; CHECK-RV32-NEXT: vmv.v.x v9, a0
+; CHECK-RV32-NEXT: li a0, 63
+; CHECK-RV32-NEXT: vand.vx v10, v9, a0
+; CHECK-RV32-NEXT: vsrl.vv v10, v8, v10
+; CHECK-RV32-NEXT: vrsub.vi v9, v9, 0
+; CHECK-RV32-NEXT: vand.vx v9, v9, a0
+; CHECK-RV32-NEXT: vsll.vv v8, v8, v9
+; CHECK-RV32-NEXT: vor.vv v8, v10, v8
+; CHECK-RV32-NEXT: ret
+;
+; CHECK-RV64-LABEL: vror_vx_v1i64:
+; CHECK-RV64: # %bb.0:
+; CHECK-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; CHECK-RV64-NEXT: vmv.s.x v9, a0
+; CHECK-RV64-NEXT: li a0, 63
+; CHECK-RV64-NEXT: vand.vx v10, v9, a0
+; CHECK-RV64-NEXT: vsrl.vv v10, v8, v10
+; CHECK-RV64-NEXT: vrsub.vi v9, v9, 0
+; CHECK-RV64-NEXT: vand.vx v9, v9, a0
+; CHECK-RV64-NEXT: vsll.vv v8, v8, v9
+; CHECK-RV64-NEXT: vor.vv v8, v10, v8
+; CHECK-RV64-NEXT: ret
;
; CHECK-ZVBB-LABEL: vror_vx_v1i64:
; CHECK-ZVBB: # %bb.0:
diff --git a/llvm/test/CodeGen/RISCV/rvv/shuffle-reverse.ll b/llvm/test/CodeGen/RISCV/rvv/shuffle-reverse.ll
index 00609a17f1efc8..70b4ab2c63c100 100644
--- a/llvm/test/CodeGen/RISCV/rvv/shuffle-reverse.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/shuffle-reverse.ll
@@ -81,7 +81,7 @@ define <16 x i8> @v8i8_2(<8 x i8> %a, <8 x i8> %b) {
; CHECK-NEXT: vrsub.vi v8, v11, 7
; CHECK-NEXT: li a0, 255
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; CHECK-NEXT: vmv.v.x v0, a0
+; CHECK-NEXT: vmv.s.x v0, a0
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; CHECK-NEXT: vrgather.vv v10, v9, v8, v0.t
; CHECK-NEXT: vmv.v.v v8, v10
@@ -118,7 +118,7 @@ define <32 x i8> @v16i8_2(<16 x i8> %a, <16 x i8> %b) {
; RV32-NEXT: lui a0, 16
; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; RV32-NEXT: vmv.v.x v0, a0
+; RV32-NEXT: vmv.s.x v0, a0
; RV32-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; RV32-NEXT: vrgather.vv v10, v14, v8, v0.t
; RV32-NEXT: vmv.v.v v8, v10
@@ -138,7 +138,7 @@ define <32 x i8> @v16i8_2(<16 x i8> %a, <16 x i8> %b) {
; RV64-NEXT: lui a0, 16
; RV64-NEXT: addiw a0, a0, -1
; RV64-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; RV64-NEXT: vmv.v.x v0, a0
+; RV64-NEXT: vmv.s.x v0, a0
; RV64-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; RV64-NEXT: vrgather.vv v10, v14, v8, v0.t
; RV64-NEXT: vmv.v.v v8, v10
@@ -220,15 +220,13 @@ define <16 x i16> @v8i16_2(<8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: v8i16_2:
; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v12, v9
-; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
; CHECK-NEXT: vid.v v14
; CHECK-NEXT: vrsub.vi v16, v14, 15
; CHECK-NEXT: vrgather.vv v10, v8, v16
; CHECK-NEXT: vrsub.vi v8, v14, 7
; CHECK-NEXT: li a0, 255
-; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; CHECK-NEXT: vmv.v.x v0, a0
-; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
+; CHECK-NEXT: vmv.s.x v0, a0
; CHECK-NEXT: vrgather.vv v10, v12, v8, v0.t
; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret
@@ -265,7 +263,7 @@ define <32 x i16> @v16i16_2(<16 x i16> %a, <16 x i16> %b) {
; RV32-NEXT: lui a0, 16
; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; RV32-NEXT: vmv.v.x v0, a0
+; RV32-NEXT: vmv.s.x v0, a0
; RV32-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; RV32-NEXT: vrgather.vv v8, v20, v12, v0.t
; RV32-NEXT: ret
@@ -285,7 +283,7 @@ define <32 x i16> @v16i16_2(<16 x i16> %a, <16 x i16> %b) {
; RV64-NEXT: lui a0, 16
; RV64-NEXT: addiw a0, a0, -1
; RV64-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; RV64-NEXT: vmv.v.x v0, a0
+; RV64-NEXT: vmv.s.x v0, a0
; RV64-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; RV64-NEXT: vrgather.vv v8, v20, v12, v0.t
; RV64-NEXT: ret
@@ -369,15 +367,13 @@ define <16 x i32> @v8i32_2(<8 x i32> %a, <8 x i32> %b) {
; CHECK-LABEL: v8i32_2:
; CHECK: # %bb.0:
; CHECK-NEXT: vmv2r.v v16, v10
-; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; CHECK-NEXT: vid.v v20
; CHECK-NEXT: vrsub.vi v24, v20, 15
; CHECK-NEXT: vrgather.vv v12, v8, v24
; CHECK-NEXT: vrsub.vi v8, v20, 7
; CHECK-NEXT: li a0, 255
-; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; CHECK-NEXT: vmv.v.x v0, a0
-; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
+; CHECK-NEXT: vmv.s.x v0, a0
; CHECK-NEXT: vrgather.vv v12, v16, v8, v0.t
; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret
@@ -404,7 +400,7 @@ define <32 x i32> @v16i32_2(<16 x i32> %a, <16 x i32> %b) {
; RV32-NEXT: lui a0, %hi(.LCPI23_0)
; RV32-NEXT: addi a0, a0, %lo(.LCPI23_0)
; RV32-NEXT: li a1, 32
-; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma
+; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; RV32-NEXT: vle32.v v0, (a0)
; RV32-NEXT: vmv4r.v v24, v12
; RV32-NEXT: vmv4r.v v16, v8
@@ -413,9 +409,7 @@ define <32 x i32> @v16i32_2(<16 x i32> %a, <16 x i32> %b) {
; RV32-NEXT: vrsub.vi v16, v16, 15
; RV32-NEXT: lui a0, 16
; RV32-NEXT: addi a0, a0, -1
-; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; RV32-NEXT: vmv.v.x v0, a0
-; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, mu
+; RV32-NEXT: vmv.s.x v0, a0
; RV32-NEXT: vrgather.vv v8, v24, v16, v0.t
; RV32-NEXT: ret
;
@@ -424,7 +418,7 @@ define <32 x i32> @v16i32_2(<16 x i32> %a, <16 x i32> %b) {
; RV64-NEXT: lui a0, %hi(.LCPI23_0)
; RV64-NEXT: addi a0, a0, %lo(.LCPI23_0)
; RV64-NEXT: li a1, 32
-; RV64-NEXT: vsetvli zero, a1, e32, m8, ta, ma
+; RV64-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; RV64-NEXT: vle32.v v0, (a0)
; RV64-NEXT: vmv4r.v v24, v12
; RV64-NEXT: vmv4r.v v16, v8
@@ -433,9 +427,7 @@ define <32 x i32> @v16i32_2(<16 x i32> %a, <16 x i32> %b) {
; RV64-NEXT: vrsub.vi v16, v16, 15
; RV64-NEXT: lui a0, 16
; RV64-NEXT: addiw a0, a0, -1
-; RV64-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; RV64-NEXT: vmv.v.x v0, a0
-; RV64-NEXT: vsetvli zero, a1, e32, m8, ta, mu
+; RV64-NEXT: vmv.s.x v0, a0
; RV64-NEXT: vrgather.vv v8, v24, v16, v0.t
; RV64-NEXT: ret
%v32i32 = shufflevector <16 x i32> %a, <16 x i32> %b, <32 x i32> <i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
@@ -600,15 +592,13 @@ define <16 x half> @v8f16_2(<8 x half> %a, <8 x half> %b) {
; CHECK-LABEL: v8f16_2:
; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v12, v9
-; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
; CHECK-NEXT: vid.v v14
; CHECK-NEXT: vrsub.vi v16, v14, 15
; CHECK-NEXT: vrgather.vv v10, v8, v16
; CHECK-NEXT: vrsub.vi v8, v14, 7
; CHECK-NEXT: li a0, 255
-; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; CHECK-NEXT: vmv.v.x v0, a0
-; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
+; CHECK-NEXT: vmv.s.x v0, a0
; CHECK-NEXT: vrgather.vv v10, v12, v8, v0.t
; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret
@@ -720,15 +710,13 @@ define <16 x float> @v8f32_2(<8 x float> %a, <8 x float> %b) {
; CHECK-LABEL: v8f32_2:
; CHECK: # %bb.0:
; CHECK-NEXT: vmv2r.v v16, v10
-; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; CHECK-NEXT: vid.v v20
; CHECK-NEXT: vrsub.vi v24, v20, 15
; CHECK-NEXT: vrgather.vv v12, v8, v24
; CHECK-NEXT: vrsub.vi v8, v20, 7
; CHECK-NEXT: li a0, 255
-; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; CHECK-NEXT: vmv.v.x v0, a0
-; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
+; CHECK-NEXT: vmv.s.x v0, a0
; CHECK-NEXT: vrgather.vv v12, v16, v8, v0.t
; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
index 205965f62d3d0b..c674670d8d030a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
@@ -21,7 +21,7 @@ define {<16 x i1>, <16 x i1>} @vector_deinterleave_v16i1_v32i1(<32 x i1> %vec) {
; RV32-NEXT: lui a0, 16
; RV32-NEXT: addi a0, a0, -256
; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; RV32-NEXT: vmv.v.x v0, a0
+; RV32-NEXT: vmv.s.x v0, a0
; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; RV32-NEXT: vrgather.vv v9, v8, v12, v0.t
; RV32-NEXT: vmsne.vi v9, v9, 0
@@ -49,7 +49,7 @@ define {<16 x i1>, <16 x i1>} @vector_deinterleave_v16i1_v32i1(<32 x i1> %vec) {
; RV64-NEXT: lui a0, 16
; RV64-NEXT: addiw a0, a0, -256
; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; RV64-NEXT: vmv.v.x v0, a0
+; RV64-NEXT: vmv.s.x v0, a0
; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; RV64-NEXT: vrgather.vv v9, v8, v12, v0.t
; RV64-NEXT: vmsne.vi v9, v9, 0
diff --git a/llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll b/llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
index 9796ffa184ca86..0b3a51b12ddaeb 100644
--- a/llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
+++ b/llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
@@ -662,9 +662,7 @@ define void @test_srem_vec(ptr %X) nounwind {
; RV32MV-NEXT: vslide1down.vx v8, v8, a1
; RV32MV-NEXT: vslidedown.vi v8, v8, 2
; RV32MV-NEXT: li a0, 85
-; RV32MV-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
-; RV32MV-NEXT: vmv.v.x v0, a0
-; RV32MV-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; RV32MV-NEXT: vmv.s.x v0, a0
; RV32MV-NEXT: vmv.v.i v10, 1
; RV32MV-NEXT: vmerge.vim v10, v10, -1, v0
; RV32MV-NEXT: vand.vv v8, v8, v10
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