[llvm] aea4528 - [RISCV] Improve cost model test coverage for insert/extract element
Philip Reames via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 30 10:34:23 PDT 2023
Author: Philip Reames
Date: 2023-08-30T10:34:02-07:00
New Revision: aea452841b6448c20f2f5e4ac928f79d99963e04
URL: https://github.com/llvm/llvm-project/commit/aea452841b6448c20f2f5e4ac928f79d99963e04
DIFF: https://github.com/llvm/llvm-project/commit/aea452841b6448c20f2f5e4ac928f79d99963e04.diff
LOG: [RISCV] Improve cost model test coverage for insert/extract element
In particular, high LMULs, constant offsets within high LMUL, and types which require splitting. Note that most of these are way off with current lowering.
Added:
Modified:
llvm/test/Analysis/CostModel/RISCV/rvv-extractelement.ll
llvm/test/Analysis/CostModel/RISCV/rvv-insertelement.ll
Removed:
################################################################################
diff --git a/llvm/test/Analysis/CostModel/RISCV/rvv-extractelement.ll b/llvm/test/Analysis/CostModel/RISCV/rvv-extractelement.ll
index 6722b1cb1d68d8..c73ffa340d62b8 100644
--- a/llvm/test/Analysis/CostModel/RISCV/rvv-extractelement.ll
+++ b/llvm/test/Analysis/CostModel/RISCV/rvv-extractelement.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py
-; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=riscv32 -mattr=+v,+f,+d,+zfh,+zvfh -riscv-v-vector-bits-min=-1 < %s | FileCheck %s --check-prefixes=RV32V
-; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=riscv64 -mattr=+v,+f,+d,+zfh,+zvfh -riscv-v-vector-bits-min=-1 < %s | FileCheck %s --check-prefixes=RV64V
-; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=riscv32 -mattr=+zve64x -riscv-v-vector-bits-min=-1 < %s | FileCheck %s --check-prefixes=RV32ZVE64X
-; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=riscv64 -mattr=+zve64x -riscv-v-vector-bits-min=-1 < %s | FileCheck %s --check-prefixes=RV64ZVE64X
+; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=riscv32 -mattr=+v,+f,+d,+zfh,+zvfh < %s | FileCheck %s --check-prefixes=RV32V
+; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=riscv64 -mattr=+v,+f,+d,+zfh,+zvfh < %s | FileCheck %s --check-prefixes=RV64V
+; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=riscv32 -mattr=+zve64x < %s | FileCheck %s --check-prefixes=RV32ZVE64X
+; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=riscv64 -mattr=+zve64x < %s | FileCheck %s --check-prefixes=RV64ZVE64X
; Check that we don't crash querying costs when vectors are not enabled.
; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=riscv64
@@ -862,6 +862,98 @@ define void @extractelement_int(i32 %x) {
ret void
}
+; Cover high lmul extracts and types which require splitting
+define void @extractelement_int_lmul(i32 %x) {
+; RV32V-LABEL: 'extractelement_int_lmul'
+; RV32V-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v128i8_31 = extractelement <128 x i8> undef, i32 31
+; RV32V-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v128i8_63 = extractelement <128 x i8> undef, i32 63
+; RV32V-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v128i8_127 = extractelement <128 x i8> undef, i32 127
+; RV32V-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v256i8_127 = extractelement <256 x i8> undef, i32 127
+; RV32V-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v256i8_255 = extractelement <256 x i8> undef, i32 255
+; RV32V-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v32i32_3 = extractelement <32 x i32> undef, i32 3
+; RV32V-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v32i32_7 = extractelement <32 x i32> undef, i32 7
+; RV32V-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v32i32_15 = extractelement <32 x i32> undef, i32 15
+; RV32V-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v32i32_31 = extractelement <32 x i32> undef, i32 31
+; RV32V-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v64i32_63 = extractelement <64 x i32> undef, i32 63
+; RV32V-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v128i8 = extractelement <128 x i8> undef, i32 %x
+; RV32V-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v256i8 = extractelement <256 x i8> undef, i32 %x
+; RV32V-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v32i32 = extractelement <32 x i32> undef, i32 %x
+; RV32V-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v64i32 = extractelement <64 x i32> undef, i32 %x
+; RV32V-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
+;
+; RV64V-LABEL: 'extractelement_int_lmul'
+; RV64V-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v128i8_31 = extractelement <128 x i8> undef, i32 31
+; RV64V-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v128i8_63 = extractelement <128 x i8> undef, i32 63
+; RV64V-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v128i8_127 = extractelement <128 x i8> undef, i32 127
+; RV64V-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v256i8_127 = extractelement <256 x i8> undef, i32 127
+; RV64V-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v256i8_255 = extractelement <256 x i8> undef, i32 255
+; RV64V-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v32i32_3 = extractelement <32 x i32> undef, i32 3
+; RV64V-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v32i32_7 = extractelement <32 x i32> undef, i32 7
+; RV64V-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v32i32_15 = extractelement <32 x i32> undef, i32 15
+; RV64V-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v32i32_31 = extractelement <32 x i32> undef, i32 31
+; RV64V-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v64i32_63 = extractelement <64 x i32> undef, i32 63
+; RV64V-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v128i8 = extractelement <128 x i8> undef, i32 %x
+; RV64V-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v256i8 = extractelement <256 x i8> undef, i32 %x
+; RV64V-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v32i32 = extractelement <32 x i32> undef, i32 %x
+; RV64V-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v64i32 = extractelement <64 x i32> undef, i32 %x
+; RV64V-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
+;
+; RV32ZVE64X-LABEL: 'extractelement_int_lmul'
+; RV32ZVE64X-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v128i8_31 = extractelement <128 x i8> undef, i32 31
+; RV32ZVE64X-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v128i8_63 = extractelement <128 x i8> undef, i32 63
+; RV32ZVE64X-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v128i8_127 = extractelement <128 x i8> undef, i32 127
+; RV32ZVE64X-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v256i8_127 = extractelement <256 x i8> undef, i32 127
+; RV32ZVE64X-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v256i8_255 = extractelement <256 x i8> undef, i32 255
+; RV32ZVE64X-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v32i32_3 = extractelement <32 x i32> undef, i32 3
+; RV32ZVE64X-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v32i32_7 = extractelement <32 x i32> undef, i32 7
+; RV32ZVE64X-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v32i32_15 = extractelement <32 x i32> undef, i32 15
+; RV32ZVE64X-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v32i32_31 = extractelement <32 x i32> undef, i32 31
+; RV32ZVE64X-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v64i32_63 = extractelement <64 x i32> undef, i32 63
+; RV32ZVE64X-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v128i8 = extractelement <128 x i8> undef, i32 %x
+; RV32ZVE64X-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v256i8 = extractelement <256 x i8> undef, i32 %x
+; RV32ZVE64X-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v32i32 = extractelement <32 x i32> undef, i32 %x
+; RV32ZVE64X-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v64i32 = extractelement <64 x i32> undef, i32 %x
+; RV32ZVE64X-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
+;
+; RV64ZVE64X-LABEL: 'extractelement_int_lmul'
+; RV64ZVE64X-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v128i8_31 = extractelement <128 x i8> undef, i32 31
+; RV64ZVE64X-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v128i8_63 = extractelement <128 x i8> undef, i32 63
+; RV64ZVE64X-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v128i8_127 = extractelement <128 x i8> undef, i32 127
+; RV64ZVE64X-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v256i8_127 = extractelement <256 x i8> undef, i32 127
+; RV64ZVE64X-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v256i8_255 = extractelement <256 x i8> undef, i32 255
+; RV64ZVE64X-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v32i32_3 = extractelement <32 x i32> undef, i32 3
+; RV64ZVE64X-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v32i32_7 = extractelement <32 x i32> undef, i32 7
+; RV64ZVE64X-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v32i32_15 = extractelement <32 x i32> undef, i32 15
+; RV64ZVE64X-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v32i32_31 = extractelement <32 x i32> undef, i32 31
+; RV64ZVE64X-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v64i32_63 = extractelement <64 x i32> undef, i32 63
+; RV64ZVE64X-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v128i8 = extractelement <128 x i8> undef, i32 %x
+; RV64ZVE64X-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v256i8 = extractelement <256 x i8> undef, i32 %x
+; RV64ZVE64X-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v32i32 = extractelement <32 x i32> undef, i32 %x
+; RV64ZVE64X-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v64i32 = extractelement <64 x i32> undef, i32 %x
+; RV64ZVE64X-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
+;
+ %v128i8_31 = extractelement <128 x i8> undef, i32 31
+ %v128i8_63 = extractelement <128 x i8> undef, i32 63
+ %v128i8_127 = extractelement <128 x i8> undef, i32 127
+ %v256i8_127 = extractelement <256 x i8> undef, i32 127
+ %v256i8_255 = extractelement <256 x i8> undef, i32 255
+
+ %v32i32_3 = extractelement <32 x i32> undef, i32 3
+ %v32i32_7 = extractelement <32 x i32> undef, i32 7
+ %v32i32_15 = extractelement <32 x i32> undef, i32 15
+ %v32i32_31 = extractelement <32 x i32> undef, i32 31
+ %v64i32_63 = extractelement <64 x i32> undef, i32 63
+
+
+ %v128i8 = extractelement <128 x i8> undef, i32 %x
+ %v256i8 = extractelement <256 x i8> undef, i32 %x
+
+ %v32i32 = extractelement <32 x i32> undef, i32 %x
+ %v64i32 = extractelement <64 x i32> undef, i32 %x
+
+ ret void
+}
+
define void @extractelement_fp(i32 %x) {
; RV32V-LABEL: 'extractelement_fp'
; RV32V-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2f16_0 = extractelement <2 x half> undef, i32 0
diff --git a/llvm/test/Analysis/CostModel/RISCV/rvv-insertelement.ll b/llvm/test/Analysis/CostModel/RISCV/rvv-insertelement.ll
index 8e124480b2ea74..125580f67b876d 100644
--- a/llvm/test/Analysis/CostModel/RISCV/rvv-insertelement.ll
+++ b/llvm/test/Analysis/CostModel/RISCV/rvv-insertelement.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py
-; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=riscv32 -mattr=+v,+f,+d,+zfh,+zvfh -riscv-v-vector-bits-min=-1 < %s | FileCheck %s --check-prefixes=RV32V
-; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=riscv64 -mattr=+v,+f,+d,+zfh,+zvfh -riscv-v-vector-bits-min=-1 < %s | FileCheck %s --check-prefixes=RV64V
-; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=riscv32 -mattr=+zve64x -riscv-v-vector-bits-min=-1 < %s | FileCheck %s --check-prefixes=RV32ZVE64X
-; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=riscv64 -mattr=+zve64x -riscv-v-vector-bits-min=-1 < %s | FileCheck %s --check-prefixes=RV64ZVE64X
+; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=riscv32 -mattr=+v,+f,+d,+zfh,+zvfh < %s | FileCheck %s --check-prefixes=RV32V
+; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=riscv64 -mattr=+v,+f,+d,+zfh,+zvfh < %s | FileCheck %s --check-prefixes=RV64V
+; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=riscv32 -mattr=+zve64x < %s | FileCheck %s --check-prefixes=RV32ZVE64X
+; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=riscv64 -mattr=+zve64x < %s | FileCheck %s --check-prefixes=RV64ZVE64X
; Check that we don't crash querying costs when vectors are not enabled.
; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=riscv64
@@ -862,6 +862,98 @@ define void @insertelement_int(i32 %x) {
ret void
}
+; Cover high lmul extracts and types which require splitting
+define void @insertelement_int_lmul(i32 %x) {
+; RV32V-LABEL: 'insertelement_int_lmul'
+; RV32V-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v128i8_31 = insertelement <128 x i8> undef, i8 undef, i32 31
+; RV32V-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v128i8_63 = insertelement <128 x i8> undef, i8 undef, i32 63
+; RV32V-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v128i8_127 = insertelement <128 x i8> undef, i8 undef, i32 127
+; RV32V-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v256i8_127 = insertelement <256 x i8> undef, i8 undef, i32 127
+; RV32V-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v256i8_255 = insertelement <256 x i8> undef, i8 undef, i32 255
+; RV32V-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v32i32_3 = insertelement <32 x i32> undef, i32 undef, i32 3
+; RV32V-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v32i32_7 = insertelement <32 x i32> undef, i32 undef, i32 7
+; RV32V-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v32i32_15 = insertelement <32 x i32> undef, i32 undef, i32 15
+; RV32V-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v32i32_31 = insertelement <32 x i32> undef, i32 undef, i32 31
+; RV32V-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v64i32_63 = insertelement <64 x i32> undef, i32 undef, i32 63
+; RV32V-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v128i8 = insertelement <128 x i8> undef, i8 undef, i32 %x
+; RV32V-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v256i8 = insertelement <256 x i8> undef, i8 undef, i32 %x
+; RV32V-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v32i32 = insertelement <32 x i32> undef, i32 undef, i32 %x
+; RV32V-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v64i32 = insertelement <64 x i32> undef, i32 undef, i32 %x
+; RV32V-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
+;
+; RV64V-LABEL: 'insertelement_int_lmul'
+; RV64V-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v128i8_31 = insertelement <128 x i8> undef, i8 undef, i32 31
+; RV64V-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v128i8_63 = insertelement <128 x i8> undef, i8 undef, i32 63
+; RV64V-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v128i8_127 = insertelement <128 x i8> undef, i8 undef, i32 127
+; RV64V-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v256i8_127 = insertelement <256 x i8> undef, i8 undef, i32 127
+; RV64V-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v256i8_255 = insertelement <256 x i8> undef, i8 undef, i32 255
+; RV64V-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v32i32_3 = insertelement <32 x i32> undef, i32 undef, i32 3
+; RV64V-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v32i32_7 = insertelement <32 x i32> undef, i32 undef, i32 7
+; RV64V-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v32i32_15 = insertelement <32 x i32> undef, i32 undef, i32 15
+; RV64V-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v32i32_31 = insertelement <32 x i32> undef, i32 undef, i32 31
+; RV64V-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v64i32_63 = insertelement <64 x i32> undef, i32 undef, i32 63
+; RV64V-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v128i8 = insertelement <128 x i8> undef, i8 undef, i32 %x
+; RV64V-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v256i8 = insertelement <256 x i8> undef, i8 undef, i32 %x
+; RV64V-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v32i32 = insertelement <32 x i32> undef, i32 undef, i32 %x
+; RV64V-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v64i32 = insertelement <64 x i32> undef, i32 undef, i32 %x
+; RV64V-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
+;
+; RV32ZVE64X-LABEL: 'insertelement_int_lmul'
+; RV32ZVE64X-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v128i8_31 = insertelement <128 x i8> undef, i8 undef, i32 31
+; RV32ZVE64X-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v128i8_63 = insertelement <128 x i8> undef, i8 undef, i32 63
+; RV32ZVE64X-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v128i8_127 = insertelement <128 x i8> undef, i8 undef, i32 127
+; RV32ZVE64X-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v256i8_127 = insertelement <256 x i8> undef, i8 undef, i32 127
+; RV32ZVE64X-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v256i8_255 = insertelement <256 x i8> undef, i8 undef, i32 255
+; RV32ZVE64X-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v32i32_3 = insertelement <32 x i32> undef, i32 undef, i32 3
+; RV32ZVE64X-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v32i32_7 = insertelement <32 x i32> undef, i32 undef, i32 7
+; RV32ZVE64X-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v32i32_15 = insertelement <32 x i32> undef, i32 undef, i32 15
+; RV32ZVE64X-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v32i32_31 = insertelement <32 x i32> undef, i32 undef, i32 31
+; RV32ZVE64X-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v64i32_63 = insertelement <64 x i32> undef, i32 undef, i32 63
+; RV32ZVE64X-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v128i8 = insertelement <128 x i8> undef, i8 undef, i32 %x
+; RV32ZVE64X-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v256i8 = insertelement <256 x i8> undef, i8 undef, i32 %x
+; RV32ZVE64X-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v32i32 = insertelement <32 x i32> undef, i32 undef, i32 %x
+; RV32ZVE64X-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v64i32 = insertelement <64 x i32> undef, i32 undef, i32 %x
+; RV32ZVE64X-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
+;
+; RV64ZVE64X-LABEL: 'insertelement_int_lmul'
+; RV64ZVE64X-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v128i8_31 = insertelement <128 x i8> undef, i8 undef, i32 31
+; RV64ZVE64X-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v128i8_63 = insertelement <128 x i8> undef, i8 undef, i32 63
+; RV64ZVE64X-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v128i8_127 = insertelement <128 x i8> undef, i8 undef, i32 127
+; RV64ZVE64X-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v256i8_127 = insertelement <256 x i8> undef, i8 undef, i32 127
+; RV64ZVE64X-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v256i8_255 = insertelement <256 x i8> undef, i8 undef, i32 255
+; RV64ZVE64X-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v32i32_3 = insertelement <32 x i32> undef, i32 undef, i32 3
+; RV64ZVE64X-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v32i32_7 = insertelement <32 x i32> undef, i32 undef, i32 7
+; RV64ZVE64X-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v32i32_15 = insertelement <32 x i32> undef, i32 undef, i32 15
+; RV64ZVE64X-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v32i32_31 = insertelement <32 x i32> undef, i32 undef, i32 31
+; RV64ZVE64X-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v64i32_63 = insertelement <64 x i32> undef, i32 undef, i32 63
+; RV64ZVE64X-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v128i8 = insertelement <128 x i8> undef, i8 undef, i32 %x
+; RV64ZVE64X-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v256i8 = insertelement <256 x i8> undef, i8 undef, i32 %x
+; RV64ZVE64X-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v32i32 = insertelement <32 x i32> undef, i32 undef, i32 %x
+; RV64ZVE64X-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v64i32 = insertelement <64 x i32> undef, i32 undef, i32 %x
+; RV64ZVE64X-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
+;
+ %v128i8_31 = insertelement <128 x i8> undef, i8 undef, i32 31
+ %v128i8_63 = insertelement <128 x i8> undef, i8 undef, i32 63
+ %v128i8_127 = insertelement <128 x i8> undef, i8 undef, i32 127
+ %v256i8_127 = insertelement <256 x i8> undef, i8 undef, i32 127
+ %v256i8_255 = insertelement <256 x i8> undef, i8 undef, i32 255
+
+ %v32i32_3 = insertelement <32 x i32> undef, i32 undef, i32 3
+ %v32i32_7 = insertelement <32 x i32> undef, i32 undef, i32 7
+ %v32i32_15 = insertelement <32 x i32> undef, i32 undef, i32 15
+ %v32i32_31 = insertelement <32 x i32> undef, i32 undef, i32 31
+ %v64i32_63 = insertelement <64 x i32> undef, i32 undef, i32 63
+
+
+ %v128i8 = insertelement <128 x i8> undef, i8 undef, i32 %x
+ %v256i8 = insertelement <256 x i8> undef, i8 undef, i32 %x
+
+ %v32i32 = insertelement <32 x i32> undef, i32 undef, i32 %x
+ %v64i32 = insertelement <64 x i32> undef, i32 undef, i32 %x
+
+ ret void
+}
+
define void @insertelement_fp(i32 %x) {
; RV32V-LABEL: 'insertelement_fp'
; RV32V-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2f16_0 = insertelement <2 x half> undef, half undef, i32 0
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