[PATCH] D158492: [RISCV] Add CSR RegisterClass and save/restore fcsr in interrupt

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:549
+      BuildMI(MBB, I, DL, get(RISCV::CSRRS))
+          .addReg(RISCV::X5, RegState::Define)
+          .addImm(getSysRegEncoding(SrcReg))
----------------
wangpc wrote:
> craig.topper wrote:
> > This seems tricky to me to hardcode a GPR in here. This makes the code only work in certain scenarios. Do other targets do anything like this?
> > This seems tricky to me to hardcode a GPR in here.
> We just need a GPR to store the value of CSRs.
> > This makes the code only work in certain scenarios. 
> I don't get it. This code is only for saving CSRs.
> > Do other targets do anything like this?
> No, I haven't find any target doing this.
> > This seems tricky to me to hardcode a GPR in here.
> We just need a GPR to store the value of CSRs.
> > This makes the code only work in certain scenarios. 
> I don't get it. This code is only for saving CSRs.

It only works in the prolog and epilogue where that GPR is available. loadRegFromStackSlot and storeRegToStackSlot are normally also used for spills and reloads, but that wouldn’t work if we ever needed that for CSRs.




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Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:600
 def FRM    : RISCVReg<0, "frm">;
+def FCSR   : RISCVReg<0, "fcsr">;
+
----------------
This overlaps with FRM and FFLAGS. Probably at least deserves a comment about why they aren’t subregs.


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  https://reviews.llvm.org/D158492/new/

https://reviews.llvm.org/D158492