[PATCH] D159080: [mlir][ArmSME] Fix get_tile_id type in zero lowering

[Cullen Rhodes via Phabricator via llvm-commits]

c-rhodes marked an inline comment as done.
c-rhodes added inline comments.


================
Comment at: mlir/test/Dialect/ArmSME/tile-zero-masks.mlir:6
 
+// This test verifies the 8-bit tile mask operand of the zero intrinsic zeroes
+// the correct tiles. Both integer and floating-point datatypes are checked.
----------------
awarzynski wrote:
> c-rhodes wrote:
> > c-rhodes wrote:
> > > awarzynski wrote:
> > > > How is "8-bit" relevant here? What's meant to be 8-bit?
> > > > How is "8-bit" relevant here? What's meant to be 8-bit?
> > > 
> > > the zero instruction mask, see https://armv8.arm.com/latest_builds/v9A/isa64/zero_za_i.xml
> > > > How is "8-bit" relevant here? What's meant to be 8-bit?
> > > 
> > > the zero instruction mask, see https://armv8.arm.com/latest_builds/v9A/isa64/zero_za_i.xml
> > 
> > Apologies that's an internal link, external link: https://developer.arm.com/documentation/ddi0602/2022-06/SME-Instructions/ZERO--Zero-a-list-of-64-bit-element-ZA-tiles-
> Thanks, now I see what you meant! 
> 
> It's a bit confusing that this is referring to "8-bit" tile masks, but there are no 8-bit tile masks here :) Perhaps:
> 
> ```
> // This test verifies the tile mask operand of the zero intrinsic zeroes
> // the correct tiles. Both integer and floating-point datatypes are checked.
> // Note that once lowered to ASM/machine code, these masks are narrowed to 8 bit:
> //   * https://developer.arm.com/documentation/ddi0602/2022-06/SME-Instructions/ZERO--Zero-a-list-of-64-bit-element-ZA-tiles-
> ```
> 
> WDYT? Did I get it right?
I've just removed mention of 8-bit mask altogether


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https://reviews.llvm.org/D159080