[PATCH] D158913: [RISCV] Add a cross basic block VXRM write insertion pass.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInsertWriteVXRM.cpp:275
+            .addImm(NewVXRMImm);
+        MI.addOperand(MachineOperand::CreateReg(RISCV::VXRM, /*IsDef*/ false,
+                                                /*IsImp*/ true));
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This is a bug, we need to add the operand even if we don't emit WriteVXRMImm


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D158913/new/

https://reviews.llvm.org/D158913