[PATCH] D156390: [SDAG][RISCV] Avoid expanding is-power-of-2 pattern on riscv32/64 with zbb

[Yingwei Zheng via Phabricator via llvm-commits]

dtcxzyw added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/rvv/ctpop-sdnode.ll:1512
+
+define <8 x i64> @ctpop_v8i64(<8 x i64> %va) {
+; RV32-LABEL: ctpop_v8i64:
----------------
These fixed-vector tests should be moved into fixed-vectors-ctpop.ll.



Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D156390/new/

https://reviews.llvm.org/D156390