[PATCH] D158759: [RISCV] Add a pass to rewrite rd to x0 for non-computational instrs whose return values are unused

Philip Reames via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Aug 29 12:04:48 PDT 2023

reames added a comment.

At a macro level, this could be generalized to be target independent (as AArch64 also has a zero register), but I support generalizing this within RISCV first.

Comment at: llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp:65
+    for (MachineInstr &MI : MBB) {
+      // We only handle non-computational instructions since some NOP encodings
+      // are reserved for HINT instructions.
I don't think we need to worry about the reserved nops, as they won't have an MI representation will they?  Unless we've implemented one, and we could just guard explicitly for the reserved nop cases?

Comment at: llvm/lib/Target/RISCV/RISCVTargetMachine.cpp:402
+  }
If you place your new pass after InsertVSETVLI, you should be able to delete this block of code from that pass.

  // Once we're fully done rewriting all the instructions, do a final pass
  // through to check for VSETVLIs which write to an unused destination.
  // For the non X0, X0 variant, we can replace the destination register
  // with X0 to reduce register pressure.  This is really a generic
  // optimization which can be applied to any dead def (TODO: generalize).
  for (MachineBasicBlock &MBB : MF) {
    for (MachineInstr &MI : MBB) {
      if (MI.getOpcode() == RISCV::PseudoVSETVLI ||
          MI.getOpcode() == RISCV::PseudoVSETIVLI) {
        Register VRegDef = MI.getOperand(0).getReg();
        if (VRegDef != RISCV::X0 && MRI->use_nodbg_empty(VRegDef))


Comment at: llvm/test/CodeGen/RISCV/atomic-rmw-discard.ll:1
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -O3 -mtriple=riscv32 -mattr=+a -verify-machineinstrs < %s \
Please go ahead and precommit the new test file so that we can see the change being made in this review.  

  rG LLVM Github Monorepo



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