[PATCH] D158853: [SDAG] Add SimplifyDemandedBits support for ISD::SPLAT_VECTOR_PARTS

[Luke Lau via Phabricator via llvm-commits]

luke added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/rvv/vnsrl-sdnode.ll:644
   %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
   %vb = trunc <vscale x 1 x i64> %splat to <vscale x 1 x i32>
   %x = lshr <vscale x 1 x i32> %va, %vb
----------------
craig.topper wrote:
> craig.topper wrote:
> > This looks like what we really have is a missing combine on trunc of splat_vector.
> Not objecting to this patch just that it might not show the proper motivation.
Is the combine you're referring to something like:

```
              t4: i32,ch = CopyFromReg t0, Register:i32 %1
              t6: i32,ch = CopyFromReg t0, Register:i32 %2
            t8: i64 = build_pair t4, t6
          t11: nxv1i64 = splat_vector t8
        t13: nxv1i32 = truncate t11
```

to

```
              t4: i32,ch = CopyFromReg t0, Register:i32 %1
        t13: nxv1i32 = splat_vector t4
```

And not on splat_vector_parts after legalisation?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D158853/new/

https://reviews.llvm.org/D158853