[PATCH] D158463: [AMDGPU] Add IR-level pass to rewrite away address space 7

Piotr Sobczak via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Aug 29 06:03:26 PDT 2023

piotr added a comment.

Thanks for working on this. Just a few high-level comments:

  Does *not* handle memcpy() and friends (this is future work)

Heads-up - there is an open PR discussing their removal from the LLPC pass (https://github.com/GPUOpen-Drivers/llpc/pull/2518).

  (One question for reviewers: is the new pass is the right place? Should it be later in the pipeline?)

When I was considering this a while ago, I thought the pass could be placed as late as possible to take as much advantage of generic load/store handling as possible. I would say at least after CodeGenPrepare (-codegenprepare) to take advantage of addressing mode matching (see also loosely related D137066 <https://reviews.llvm.org/D137066>). Is there a particular reason for the placement as in the patch?

Comment at: llvm/lib/Target/AMDGPU/AMDGPULowerBufferFatPointers.cpp:1224
+  if (isa<LoadInst>(I))
+    // TODO: Do we need to do something about atomic loads?
+    IID = Intrinsic::amdgcn_raw_ptr_buffer_load;
krzysz00 wrote:
> @nhaehnle Upstream atomic_load from graphics?
This is D138786 (but appears to have stalled).

  rG LLVM Github Monorepo



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