[llvm] 30b6b27 - [LoongArch] Fix typos. NFC
via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 29 04:34:34 PDT 2023
Author: wanglei
Date: 2023-08-29T19:17:52+08:00
New Revision: 30b6b27385f8ddc550df54a097434a121ae56d12
URL: https://github.com/llvm/llvm-project/commit/30b6b27385f8ddc550df54a097434a121ae56d12
DIFF: https://github.com/llvm/llvm-project/commit/30b6b27385f8ddc550df54a097434a121ae56d12.diff
LOG: [LoongArch] Fix typos. NFC
Added:
Modified:
llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
index a3afd4789dfc2d..947950be2b8f35 100644
--- a/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
+++ b/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
@@ -1545,10 +1545,10 @@ foreach Inst = ["XVEXTH_Q_D", "XVEXTH_QU_DU", "XVMSKLTZ_D",
// Pat<(Intrinsic timm:$imm)
// (LAInst timm:$imm)>;
def : Pat<(int_loongarch_lasx_xvldi timm:$imm),
- (XVLDI (to_valide_timm timm:$imm))>;
+ (XVLDI (to_valid_timm timm:$imm))>;
foreach Inst = ["XVREPLI_B", "XVREPLI_H", "XVREPLI_W", "XVREPLI_D"] in
def : Pat<(deriveLASXIntrinsic<Inst>.ret timm:$imm),
- (!cast<LAInst>("Pseudo"#Inst) (to_valide_timm timm:$imm))>;
+ (!cast<LAInst>("Pseudo"#Inst) (to_valid_timm timm:$imm))>;
// vty: v32i8/v16i16/v8i32/v4i64
// Pat<(Intrinsic vty:$xj, timm:$imm)
@@ -1558,25 +1558,25 @@ foreach Inst = ["XVSAT_B", "XVSAT_BU", "XVNORI_B", "XVROTRI_B", "XVSLLWIL_H_B",
"XVSEQI_B", "XVSLEI_B", "XVSLEI_BU", "XVSLTI_B", "XVSLTI_BU",
"XVREPL128VEI_B", "XVBSLL_V", "XVBSRL_V", "XVSHUF4I_B"] in
def : Pat<(deriveLASXIntrinsic<Inst>.ret (v32i8 LASX256:$xj), timm:$imm),
- (!cast<LAInst>(Inst) LASX256:$xj, (to_valide_timm timm:$imm))>;
+ (!cast<LAInst>(Inst) LASX256:$xj, (to_valid_timm timm:$imm))>;
foreach Inst = ["XVSAT_H", "XVSAT_HU", "XVROTRI_H", "XVSLLWIL_W_H",
"XVSLLWIL_WU_HU", "XVSRLRI_H", "XVSRARI_H",
"XVSEQI_H", "XVSLEI_H", "XVSLEI_HU", "XVSLTI_H", "XVSLTI_HU",
"XVREPL128VEI_H", "XVSHUF4I_H"] in
def : Pat<(deriveLASXIntrinsic<Inst>.ret (v16i16 LASX256:$xj), timm:$imm),
- (!cast<LAInst>(Inst) LASX256:$xj, (to_valide_timm timm:$imm))>;
+ (!cast<LAInst>(Inst) LASX256:$xj, (to_valid_timm timm:$imm))>;
foreach Inst = ["XVSAT_W", "XVSAT_WU", "XVROTRI_W", "XVSLLWIL_D_W",
"XVSLLWIL_DU_WU", "XVSRLRI_W", "XVSRARI_W",
"XVSEQI_W", "XVSLEI_W", "XVSLEI_WU", "XVSLTI_W", "XVSLTI_WU",
"XVREPL128VEI_W", "XVSHUF4I_W", "XVPICKVE_W"] in
def : Pat<(deriveLASXIntrinsic<Inst>.ret (v8i32 LASX256:$xj), timm:$imm),
- (!cast<LAInst>(Inst) LASX256:$xj, (to_valide_timm timm:$imm))>;
+ (!cast<LAInst>(Inst) LASX256:$xj, (to_valid_timm timm:$imm))>;
foreach Inst = ["XVSAT_D", "XVSAT_DU", "XVROTRI_D", "XVSRLRI_D", "XVSRARI_D",
"XVSEQI_D", "XVSLEI_D", "XVSLEI_DU", "XVSLTI_D", "XVSLTI_DU",
"XVPICKVE2GR_D", "XVPICKVE2GR_DU",
"XVREPL128VEI_D", "XVPERMI_D", "XVPICKVE_D"] in
def : Pat<(deriveLASXIntrinsic<Inst>.ret (v4i64 LASX256:$xj), timm:$imm),
- (!cast<LAInst>(Inst) LASX256:$xj, (to_valide_timm timm:$imm))>;
+ (!cast<LAInst>(Inst) LASX256:$xj, (to_valid_timm timm:$imm))>;
// vty: v32i8/v16i16/v8i32/v4i64
// Pat<(Intrinsic vty:$xd, vty:$xj, timm:$imm)
@@ -1588,7 +1588,7 @@ foreach Inst = ["XVSRLNI_B_H", "XVSRANI_B_H", "XVSRLRNI_B_H", "XVSRARNI_B_H",
def : Pat<(deriveLASXIntrinsic<Inst>.ret
(v32i8 LASX256:$xd), (v32i8 LASX256:$xj), timm:$imm),
(!cast<LAInst>(Inst) LASX256:$xd, LASX256:$xj,
- (to_valide_timm timm:$imm))>;
+ (to_valid_timm timm:$imm))>;
foreach Inst = ["XVSRLNI_H_W", "XVSRANI_H_W", "XVSRLRNI_H_W", "XVSRARNI_H_W",
"XVSSRLNI_H_W", "XVSSRANI_H_W", "XVSSRLNI_HU_W", "XVSSRANI_HU_W",
"XVSSRLRNI_H_W", "XVSSRARNI_H_W", "XVSSRLRNI_HU_W", "XVSSRARNI_HU_W",
@@ -1596,7 +1596,7 @@ foreach Inst = ["XVSRLNI_H_W", "XVSRANI_H_W", "XVSRLRNI_H_W", "XVSRARNI_H_W",
def : Pat<(deriveLASXIntrinsic<Inst>.ret
(v16i16 LASX256:$xd), (v16i16 LASX256:$xj), timm:$imm),
(!cast<LAInst>(Inst) LASX256:$xd, LASX256:$xj,
- (to_valide_timm timm:$imm))>;
+ (to_valid_timm timm:$imm))>;
foreach Inst = ["XVSRLNI_W_D", "XVSRANI_W_D", "XVSRLRNI_W_D", "XVSRARNI_W_D",
"XVSSRLNI_W_D", "XVSSRANI_W_D", "XVSSRLNI_WU_D", "XVSSRANI_WU_D",
"XVSSRLRNI_W_D", "XVSSRARNI_W_D", "XVSSRLRNI_WU_D", "XVSSRARNI_WU_D",
@@ -1604,7 +1604,7 @@ foreach Inst = ["XVSRLNI_W_D", "XVSRANI_W_D", "XVSRLRNI_W_D", "XVSRARNI_W_D",
def : Pat<(deriveLASXIntrinsic<Inst>.ret
(v8i32 LASX256:$xd), (v8i32 LASX256:$xj), timm:$imm),
(!cast<LAInst>(Inst) LASX256:$xd, LASX256:$xj,
- (to_valide_timm timm:$imm))>;
+ (to_valid_timm timm:$imm))>;
foreach Inst = ["XVSRLNI_D_Q", "XVSRANI_D_Q", "XVSRLRNI_D_Q", "XVSRARNI_D_Q",
"XVSSRLNI_D_Q", "XVSSRANI_D_Q", "XVSSRLNI_DU_Q", "XVSSRANI_DU_Q",
"XVSSRLRNI_D_Q", "XVSSRARNI_D_Q", "XVSSRLRNI_DU_Q", "XVSSRARNI_DU_Q",
@@ -1612,7 +1612,7 @@ foreach Inst = ["XVSRLNI_D_Q", "XVSRANI_D_Q", "XVSRLRNI_D_Q", "XVSRARNI_D_Q",
def : Pat<(deriveLASXIntrinsic<Inst>.ret
(v4i64 LASX256:$xd), (v4i64 LASX256:$xj), timm:$imm),
(!cast<LAInst>(Inst) LASX256:$xd, LASX256:$xj,
- (to_valide_timm timm:$imm))>;
+ (to_valid_timm timm:$imm))>;
// vty: v32i8/v16i16/v8i32/v4i64
// Pat<(Intrinsic vty:$xd, vty:$xj, vty:$xk),
@@ -1693,42 +1693,42 @@ foreach Inst = ["XVFLOGB_D", "XVFCLASS_D", "XVFSQRT_D", "XVFRECIP_D", "XVFRSQRT_
(!cast<LAInst>(Inst) LASX256:$xj)>;
def : Pat<(int_loongarch_lasx_xvpickve_w_f v8f32:$xj, timm:$imm),
- (XVPICKVE_W v8f32:$xj, (to_valide_timm timm:$imm))>;
+ (XVPICKVE_W v8f32:$xj, (to_valid_timm timm:$imm))>;
def : Pat<(int_loongarch_lasx_xvpickve_d_f v4f64:$xj, timm:$imm),
- (XVPICKVE_D v4f64:$xj, (to_valide_timm timm:$imm))>;
+ (XVPICKVE_D v4f64:$xj, (to_valid_timm timm:$imm))>;
// load
def : Pat<(int_loongarch_lasx_xvld GPR:$rj, timm:$imm),
- (XVLD GPR:$rj, (to_valide_timm timm:$imm))>;
+ (XVLD GPR:$rj, (to_valid_timm timm:$imm))>;
def : Pat<(int_loongarch_lasx_xvldx GPR:$rj, GPR:$rk),
(XVLDX GPR:$rj, GPR:$rk)>;
def : Pat<(int_loongarch_lasx_xvldrepl_b GPR:$rj, timm:$imm),
- (XVLDREPL_B GPR:$rj, (to_valide_timm timm:$imm))>;
+ (XVLDREPL_B GPR:$rj, (to_valid_timm timm:$imm))>;
def : Pat<(int_loongarch_lasx_xvldrepl_h GPR:$rj, timm:$imm),
- (XVLDREPL_H GPR:$rj, (to_valide_timm timm:$imm))>;
+ (XVLDREPL_H GPR:$rj, (to_valid_timm timm:$imm))>;
def : Pat<(int_loongarch_lasx_xvldrepl_w GPR:$rj, timm:$imm),
- (XVLDREPL_W GPR:$rj, (to_valide_timm timm:$imm))>;
+ (XVLDREPL_W GPR:$rj, (to_valid_timm timm:$imm))>;
def : Pat<(int_loongarch_lasx_xvldrepl_d GPR:$rj, timm:$imm),
- (XVLDREPL_D GPR:$rj, (to_valide_timm timm:$imm))>;
+ (XVLDREPL_D GPR:$rj, (to_valid_timm timm:$imm))>;
// store
def : Pat<(int_loongarch_lasx_xvst LASX256:$xd, GPR:$rj, timm:$imm),
- (XVST LASX256:$xd, GPR:$rj, (to_valide_timm timm:$imm))>;
+ (XVST LASX256:$xd, GPR:$rj, (to_valid_timm timm:$imm))>;
def : Pat<(int_loongarch_lasx_xvstx LASX256:$xd, GPR:$rj, GPR:$rk),
(XVSTX LASX256:$xd, GPR:$rj, GPR:$rk)>;
def : Pat<(int_loongarch_lasx_xvstelm_b v32i8:$xd, GPR:$rj, timm:$imm, timm:$idx),
- (XVSTELM_B v32i8:$xd, GPR:$rj, (to_valide_timm timm:$imm),
- (to_valide_timm timm:$idx))>;
+ (XVSTELM_B v32i8:$xd, GPR:$rj, (to_valid_timm timm:$imm),
+ (to_valid_timm timm:$idx))>;
def : Pat<(int_loongarch_lasx_xvstelm_h v16i16:$xd, GPR:$rj, timm:$imm, timm:$idx),
- (XVSTELM_H v16i16:$xd, GPR:$rj, (to_valide_timm timm:$imm),
- (to_valide_timm timm:$idx))>;
+ (XVSTELM_H v16i16:$xd, GPR:$rj, (to_valid_timm timm:$imm),
+ (to_valid_timm timm:$idx))>;
def : Pat<(int_loongarch_lasx_xvstelm_w v8i32:$xd, GPR:$rj, timm:$imm, timm:$idx),
- (XVSTELM_W v8i32:$xd, GPR:$rj, (to_valide_timm timm:$imm),
- (to_valide_timm timm:$idx))>;
+ (XVSTELM_W v8i32:$xd, GPR:$rj, (to_valid_timm timm:$imm),
+ (to_valid_timm timm:$idx))>;
def : Pat<(int_loongarch_lasx_xvstelm_d v4i64:$xd, GPR:$rj, timm:$imm, timm:$idx),
- (XVSTELM_D v4i64:$xd, GPR:$rj, (to_valide_timm timm:$imm),
- (to_valide_timm timm:$idx))>;
+ (XVSTELM_D v4i64:$xd, GPR:$rj, (to_valid_timm timm:$imm),
+ (to_valid_timm timm:$idx))>;
} // Predicates = [HasExtLASX]
diff --git a/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
index 13332be0bc380c..e021adcecf4dc8 100644
--- a/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
+++ b/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
@@ -145,7 +145,7 @@ def lsxsplati32 : PatFrag<(ops node:$e0),
def lsxsplati64 : PatFrag<(ops node:$e0),
(v2i64 (build_vector node:$e0, node:$e0))>;
-def to_valide_timm : SDNodeXForm<timm, [{
+def to_valid_timm : SDNodeXForm<timm, [{
auto CN = cast<ConstantSDNode>(N);
return CurDAG->getTargetConstant(CN->getSExtValue(), SDLoc(N), Subtarget->getGRLenVT());
}]>;
@@ -1639,10 +1639,10 @@ foreach Inst = ["VEXTH_Q_D", "VEXTH_QU_DU", "VMSKLTZ_D",
// Pat<(Intrinsic timm:$imm)
// (LAInst timm:$imm)>;
def : Pat<(int_loongarch_lsx_vldi timm:$imm),
- (VLDI (to_valide_timm timm:$imm))>;
+ (VLDI (to_valid_timm timm:$imm))>;
foreach Inst = ["VREPLI_B", "VREPLI_H", "VREPLI_W", "VREPLI_D"] in
def : Pat<(deriveLSXIntrinsic<Inst>.ret timm:$imm),
- (!cast<LAInst>("Pseudo"#Inst) (to_valide_timm timm:$imm))>;
+ (!cast<LAInst>("Pseudo"#Inst) (to_valid_timm timm:$imm))>;
// vty: v16i8/v8i16/v4i32/v2i64
// Pat<(Intrinsic vty:$vj, timm:$imm)
@@ -1652,25 +1652,25 @@ foreach Inst = ["VSAT_B", "VSAT_BU", "VNORI_B", "VROTRI_B", "VSLLWIL_H_B",
"VSEQI_B", "VSLEI_B", "VSLEI_BU", "VSLTI_B", "VSLTI_BU",
"VREPLVEI_B", "VBSLL_V", "VBSRL_V", "VSHUF4I_B"] in
def : Pat<(deriveLSXIntrinsic<Inst>.ret (v16i8 LSX128:$vj), timm:$imm),
- (!cast<LAInst>(Inst) LSX128:$vj, (to_valide_timm timm:$imm))>;
+ (!cast<LAInst>(Inst) LSX128:$vj, (to_valid_timm timm:$imm))>;
foreach Inst = ["VSAT_H", "VSAT_HU", "VROTRI_H", "VSLLWIL_W_H",
"VSLLWIL_WU_HU", "VSRLRI_H", "VSRARI_H",
"VSEQI_H", "VSLEI_H", "VSLEI_HU", "VSLTI_H", "VSLTI_HU",
"VREPLVEI_H", "VSHUF4I_H"] in
def : Pat<(deriveLSXIntrinsic<Inst>.ret (v8i16 LSX128:$vj), timm:$imm),
- (!cast<LAInst>(Inst) LSX128:$vj, (to_valide_timm timm:$imm))>;
+ (!cast<LAInst>(Inst) LSX128:$vj, (to_valid_timm timm:$imm))>;
foreach Inst = ["VSAT_W", "VSAT_WU", "VROTRI_W", "VSLLWIL_D_W",
"VSLLWIL_DU_WU", "VSRLRI_W", "VSRARI_W",
"VSEQI_W", "VSLEI_W", "VSLEI_WU", "VSLTI_W", "VSLTI_WU",
"VREPLVEI_W", "VSHUF4I_W"] in
def : Pat<(deriveLSXIntrinsic<Inst>.ret (v4i32 LSX128:$vj), timm:$imm),
- (!cast<LAInst>(Inst) LSX128:$vj, (to_valide_timm timm:$imm))>;
+ (!cast<LAInst>(Inst) LSX128:$vj, (to_valid_timm timm:$imm))>;
foreach Inst = ["VSAT_D", "VSAT_DU", "VROTRI_D", "VSRLRI_D", "VSRARI_D",
"VSEQI_D", "VSLEI_D", "VSLEI_DU", "VSLTI_D", "VSLTI_DU",
"VPICKVE2GR_D", "VPICKVE2GR_DU",
"VREPLVEI_D"] in
def : Pat<(deriveLSXIntrinsic<Inst>.ret (v2i64 LSX128:$vj), timm:$imm),
- (!cast<LAInst>(Inst) LSX128:$vj, (to_valide_timm timm:$imm))>;
+ (!cast<LAInst>(Inst) LSX128:$vj, (to_valid_timm timm:$imm))>;
// vty: v16i8/v8i16/v4i32/v2i64
// Pat<(Intrinsic vty:$vd, vty:$vj, timm:$imm)
@@ -1682,7 +1682,7 @@ foreach Inst = ["VSRLNI_B_H", "VSRANI_B_H", "VSRLRNI_B_H", "VSRARNI_B_H",
def : Pat<(deriveLSXIntrinsic<Inst>.ret
(v16i8 LSX128:$vd), (v16i8 LSX128:$vj), timm:$imm),
(!cast<LAInst>(Inst) LSX128:$vd, LSX128:$vj,
- (to_valide_timm timm:$imm))>;
+ (to_valid_timm timm:$imm))>;
foreach Inst = ["VSRLNI_H_W", "VSRANI_H_W", "VSRLRNI_H_W", "VSRARNI_H_W",
"VSSRLNI_H_W", "VSSRANI_H_W", "VSSRLNI_HU_W", "VSSRANI_HU_W",
"VSSRLRNI_H_W", "VSSRARNI_H_W", "VSSRLRNI_HU_W", "VSSRARNI_HU_W",
@@ -1690,7 +1690,7 @@ foreach Inst = ["VSRLNI_H_W", "VSRANI_H_W", "VSRLRNI_H_W", "VSRARNI_H_W",
def : Pat<(deriveLSXIntrinsic<Inst>.ret
(v8i16 LSX128:$vd), (v8i16 LSX128:$vj), timm:$imm),
(!cast<LAInst>(Inst) LSX128:$vd, LSX128:$vj,
- (to_valide_timm timm:$imm))>;
+ (to_valid_timm timm:$imm))>;
foreach Inst = ["VSRLNI_W_D", "VSRANI_W_D", "VSRLRNI_W_D", "VSRARNI_W_D",
"VSSRLNI_W_D", "VSSRANI_W_D", "VSSRLNI_WU_D", "VSSRANI_WU_D",
"VSSRLRNI_W_D", "VSSRARNI_W_D", "VSSRLRNI_WU_D", "VSSRARNI_WU_D",
@@ -1698,7 +1698,7 @@ foreach Inst = ["VSRLNI_W_D", "VSRANI_W_D", "VSRLRNI_W_D", "VSRARNI_W_D",
def : Pat<(deriveLSXIntrinsic<Inst>.ret
(v4i32 LSX128:$vd), (v4i32 LSX128:$vj), timm:$imm),
(!cast<LAInst>(Inst) LSX128:$vd, LSX128:$vj,
- (to_valide_timm timm:$imm))>;
+ (to_valid_timm timm:$imm))>;
foreach Inst = ["VSRLNI_D_Q", "VSRANI_D_Q", "VSRLRNI_D_Q", "VSRARNI_D_Q",
"VSSRLNI_D_Q", "VSSRANI_D_Q", "VSSRLNI_DU_Q", "VSSRANI_DU_Q",
"VSSRLRNI_D_Q", "VSSRARNI_D_Q", "VSSRLRNI_DU_Q", "VSSRARNI_DU_Q",
@@ -1706,7 +1706,7 @@ foreach Inst = ["VSRLNI_D_Q", "VSRANI_D_Q", "VSRLRNI_D_Q", "VSRARNI_D_Q",
def : Pat<(deriveLSXIntrinsic<Inst>.ret
(v2i64 LSX128:$vd), (v2i64 LSX128:$vj), timm:$imm),
(!cast<LAInst>(Inst) LSX128:$vd, LSX128:$vj,
- (to_valide_timm timm:$imm))>;
+ (to_valid_timm timm:$imm))>;
// vty: v16i8/v8i16/v4i32/v2i64
// Pat<(Intrinsic vty:$vd, vty:$vj, vty:$vk),
@@ -1788,36 +1788,36 @@ foreach Inst = ["VFLOGB_D", "VFCLASS_D", "VFSQRT_D", "VFRECIP_D", "VFRSQRT_D",
// load
def : Pat<(int_loongarch_lsx_vld GPR:$rj, timm:$imm),
- (VLD GPR:$rj, (to_valide_timm timm:$imm))>;
+ (VLD GPR:$rj, (to_valid_timm timm:$imm))>;
def : Pat<(int_loongarch_lsx_vldx GPR:$rj, GPR:$rk),
(VLDX GPR:$rj, GPR:$rk)>;
def : Pat<(int_loongarch_lsx_vldrepl_b GPR:$rj, timm:$imm),
- (VLDREPL_B GPR:$rj, (to_valide_timm timm:$imm))>;
+ (VLDREPL_B GPR:$rj, (to_valid_timm timm:$imm))>;
def : Pat<(int_loongarch_lsx_vldrepl_h GPR:$rj, timm:$imm),
- (VLDREPL_H GPR:$rj, (to_valide_timm timm:$imm))>;
+ (VLDREPL_H GPR:$rj, (to_valid_timm timm:$imm))>;
def : Pat<(int_loongarch_lsx_vldrepl_w GPR:$rj, timm:$imm),
- (VLDREPL_W GPR:$rj, (to_valide_timm timm:$imm))>;
+ (VLDREPL_W GPR:$rj, (to_valid_timm timm:$imm))>;
def : Pat<(int_loongarch_lsx_vldrepl_d GPR:$rj, timm:$imm),
- (VLDREPL_D GPR:$rj, (to_valide_timm timm:$imm))>;
+ (VLDREPL_D GPR:$rj, (to_valid_timm timm:$imm))>;
// store
def : Pat<(int_loongarch_lsx_vst LSX128:$vd, GPR:$rj, timm:$imm),
- (VST LSX128:$vd, GPR:$rj, (to_valide_timm timm:$imm))>;
+ (VST LSX128:$vd, GPR:$rj, (to_valid_timm timm:$imm))>;
def : Pat<(int_loongarch_lsx_vstx LSX128:$vd, GPR:$rj, GPR:$rk),
(VSTX LSX128:$vd, GPR:$rj, GPR:$rk)>;
def : Pat<(int_loongarch_lsx_vstelm_b v16i8:$vd, GPR:$rj, timm:$imm, timm:$idx),
- (VSTELM_B v16i8:$vd, GPR:$rj, (to_valide_timm timm:$imm),
- (to_valide_timm timm:$idx))>;
+ (VSTELM_B v16i8:$vd, GPR:$rj, (to_valid_timm timm:$imm),
+ (to_valid_timm timm:$idx))>;
def : Pat<(int_loongarch_lsx_vstelm_h v8i16:$vd, GPR:$rj, timm:$imm, timm:$idx),
- (VSTELM_H v8i16:$vd, GPR:$rj, (to_valide_timm timm:$imm),
- (to_valide_timm timm:$idx))>;
+ (VSTELM_H v8i16:$vd, GPR:$rj, (to_valid_timm timm:$imm),
+ (to_valid_timm timm:$idx))>;
def : Pat<(int_loongarch_lsx_vstelm_w v4i32:$vd, GPR:$rj, timm:$imm, timm:$idx),
- (VSTELM_W v4i32:$vd, GPR:$rj, (to_valide_timm timm:$imm),
- (to_valide_timm timm:$idx))>;
+ (VSTELM_W v4i32:$vd, GPR:$rj, (to_valid_timm timm:$imm),
+ (to_valid_timm timm:$idx))>;
def : Pat<(int_loongarch_lsx_vstelm_d v2i64:$vd, GPR:$rj, timm:$imm, timm:$idx),
- (VSTELM_D v2i64:$vd, GPR:$rj, (to_valide_timm timm:$imm),
- (to_valide_timm timm:$idx))>;
+ (VSTELM_D v2i64:$vd, GPR:$rj, (to_valid_timm timm:$imm),
+ (to_valid_timm timm:$idx))>;
} // Predicates = [HasExtLSX]
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