[llvm] 23fef2c - [RISCV] Correct scheduling information for WriteVIRedMinMaxV in RISCVSchedSiFive7.td.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-08-28T22:46:25-07:00
New Revision: 23fef2cc673a29afdd334eff70aef1adf73322d2

URL: https://github.com/llvm/llvm-project/commit/23fef2cc673a29afdd334eff70aef1adf73322d2
DIFF: https://github.com/llvm/llvm-project/commit/23fef2cc673a29afdd334eff70aef1adf73322d2.diff

LOG: [RISCV] Correct scheduling information for WriteVIRedMinMaxV in RISCVSchedSiFive7.td.

The 'let' with the Latency and Cycles from the previous defm should
apply to this one as well. Introduce a scope around the two defms.

Reviewed By: wangpc

Differential Revision: https://reviews.llvm.org/D159029

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVSchedSiFive7.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
index f1049f2b3ee741..77606f7649b8d2 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -774,11 +774,12 @@ foreach mx = SchedMxList in {
   foreach sew = SchedSEWSet<mx>.val in {
     defvar Cycles = SiFive7GetReductionCycles<mx, sew>.c;
     defvar IsWorstCase = SiFive7IsWorstCaseMXSEW<mx, sew, SchedMxList>.c;
-    let Latency = Cycles, ReleaseAtCycles = [Cycles] in
-    defm "" : LMULSEWWriteResMXSEW<"WriteVIRedV_From", [SiFive7VA],
-                                   mx, sew, IsWorstCase>;
-    defm "" : LMULSEWWriteResMXSEW<"WriteVIRedMinMaxV_From", [SiFive7VA],
-                                   mx, sew, IsWorstCase>;
+    let Latency = Cycles, ReleaseAtCycles = [Cycles] in {
+      defm "" : LMULSEWWriteResMXSEW<"WriteVIRedV_From", [SiFive7VA],
+                                     mx, sew, IsWorstCase>;
+      defm "" : LMULSEWWriteResMXSEW<"WriteVIRedMinMaxV_From", [SiFive7VA],
+                                     mx, sew, IsWorstCase>;
+    }
   }
 }