[PATCH] D158611: [AArch64] Fix arm neon vstx lane memVT size

[hstk via Phabricator via llvm-commits]

hstk30 added a comment.

So, I also want to write some test cases like `multi-vector-store-size.ll` for `load`, but I can't generate `LD` rel instrument after `instruction-select` step.

Can you give me an example?


Repository:
  rG LLVM Github Monorepo

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https://reviews.llvm.org/D158611