[PATCH] D158492: [RISCV] Add CSR RegisterClass and save/restore fcsr in interrupt

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:549
+      BuildMI(MBB, I, DL, get(RISCV::CSRRS))
+          .addReg(RISCV::X5, RegState::Define)
+          .addImm(getSysRegEncoding(SrcReg))
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This seems tricky to me to hardcode a GPR in here. This makes the code only work in certain scenarios. Do other targets do anything like this?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D158492/new/

https://reviews.llvm.org/D158492