[PATCH] D156390: [SDAG][RISCV] Avoid expanding is-power-of-2 pattern on riscv32/64 with zbb

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/rv64zbb.ll:700
 
+declare <2 x i32> @llvm.ctpop.v2i32(<2 x i32>)
+
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I meant with V and the Zvbb extensions enabled so we have vector cpop instructions.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D156390/new/

https://reviews.llvm.org/D156390