[llvm] b06f16f - [ARM][test] Test .long thumb_func - .

[Fangrui Song via llvm-commits]

Author: Fangrui Song
Date: 2023-08-26T16:28:40-07:00
New Revision: b06f16fa8108f4b8715b1df48ab5002052a24bd0

URL: https://github.com/llvm/llvm-project/commit/b06f16fa8108f4b8715b1df48ab5002052a24bd0
DIFF: https://github.com/llvm/llvm-project/commit/b06f16fa8108f4b8715b1df48ab5002052a24bd0.diff

LOG: [ARM][test] Test .long thumb_func - .

Commit 9746286beca2539438e0a6b783e106bc359036ca from 2011 is related to
a subtle case that is untested. GNU assembler produces an R_ARM_REL32
relocation.
We currently don't, therefore we have to add a workaround in MCExpr.cpp
to make the value odd (see commit 8ee6c0ea0bf30f1f1da6b49ee720b933f9676a30 "[MC] Remove isThumbFunc special case").

Added: 
    

Modified: 
    llvm/test/MC/ARM/pcrel-global.s

Removed: 
    


################################################################################
diff  --git a/llvm/test/MC/ARM/pcrel-global.s b/llvm/test/MC/ARM/pcrel-global.s
index eee51565ead9c7..91ef3b6ca7b15a 100644
--- a/llvm/test/MC/ARM/pcrel-global.s
+++ b/llvm/test/MC/ARM/pcrel-global.s
@@ -1,9 +1,21 @@
 @ RUN: llvm-mc -filetype=obj -triple=armv7 %s -o %t
 @ RUN: llvm-readelf -r %t | FileCheck %s
+@ RUN: llvm-objdump -dr --triple=armv7 %t | FileCheck %s --check-prefix=DISASM
 @ RUN: llvm-mc -filetype=obj -triple=armebv7 %s -o %t
 @ RUN: llvm-readelf -r %t | FileCheck %s
 
 @ CHECK: There are no relocations in this file.
+
+@ DISASM-LABEL: <bar>:
+@ DISASM-NEXT:    adr.w   r0, #-4
+@ DISASM-NEXT:    adr.w   r0, #-8
+@ DISASM-NEXT:    ldr.w   pc, [pc, #-0xc]         @ 0x10 <bar>
+@ DISASM-NEXT:    ldr     r0, [pc, #0x0]          @ 0x20 <bar+0x10>
+@ DISASM-NEXT:    add     r0, pc
+@ DISASM-NEXT:   .word   0xffffffef
+@@ GNU assembler creates an R_ARM_REL32 referencing bar.
+@ DISASM-NOT:    {{.}}
+
 .syntax unified
 
 .globl foo
@@ -15,9 +27,16 @@ ldr r0, foo      @ arm_ldst_pcrel_12
 
 .thumb
 .thumb_func
-
+.type bar, %function
 .globl bar
 bar:
 adr r0, bar      @ thumb_adr_pcrel_10
 adr.w r0, bar    @ t2_adr_pcrel_12
 ldr.w pc, bar    @ t2_ldst_pcrel_12
+
+  ldr r0, .LCPI
+.LPC0_1:
+  add r0, pc
+
+.LCPI:
+  .long bar-(.LPC0_1+4)  @ if there is no relocation, the value should be odd