[llvm] a6986f6 - Revert "[XCore] Remove unused TableGen classes and multiclasses"

[Brad Smith via llvm-commits]

Author: Brad Smith
Date: 2023-08-26T17:50:00-04:00
New Revision: a6986f6c14060f4cb05a4e09b0cdfb37b1186884

URL: https://github.com/llvm/llvm-project/commit/a6986f6c14060f4cb05a4e09b0cdfb37b1186884
DIFF: https://github.com/llvm/llvm-project/commit/a6986f6c14060f4cb05a4e09b0cdfb37b1186884.diff

LOG: Revert "[XCore] Remove unused TableGen classes and multiclasses"

The command line parameter added for llvm-tblgen is not valid.

This reverts commit 6b2cb3bfaa7b79fd12a6a5bb949031268285dd09.

Added: 
    

Modified: 
    llvm/lib/Target/XCore/CMakeLists.txt
    llvm/lib/Target/XCore/XCoreInstrInfo.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/XCore/CMakeLists.txt b/llvm/lib/Target/XCore/CMakeLists.txt
index c759acc626870a..447f5c54528850 100644
--- a/llvm/lib/Target/XCore/CMakeLists.txt
+++ b/llvm/lib/Target/XCore/CMakeLists.txt
@@ -4,7 +4,7 @@ set(LLVM_TARGET_DEFINITIONS XCore.td)
 
 tablegen(LLVM XCoreGenAsmWriter.inc -gen-asm-writer)
 tablegen(LLVM XCoreGenCallingConv.inc -gen-callingconv)
-tablegen(LLVM XCoreGenDAGISel.inc -gen-dag-isel -warn-on-unused-entities)
+tablegen(LLVM XCoreGenDAGISel.inc -gen-dag-isel)
 tablegen(LLVM XCoreGenDisassemblerTables.inc -gen-disassembler)
 tablegen(LLVM XCoreGenInstrInfo.inc -gen-instr-info)
 tablegen(LLVM XCoreGenRegisterInfo.inc -gen-register-info)

diff  --git a/llvm/lib/Target/XCore/XCoreInstrInfo.td b/llvm/lib/Target/XCore/XCoreInstrInfo.td
index 57158e18464a56..de1fb60a30f700 100644
--- a/llvm/lib/Target/XCore/XCoreInstrInfo.td
+++ b/llvm/lib/Target/XCore/XCoreInstrInfo.td
@@ -241,6 +241,17 @@ class F3R_np<bits<5> opc, string OpcStr> :
        !strconcat(OpcStr, " $dst, $b, $c"), []>;
 // Three operand long
 
+/// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot.
+multiclass FL3R_L2RUS<bits<9> opc1, bits<9> opc2, string OpcStr,
+                      SDNode OpNode> {
+  def _l3r: _FL3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
+                  !strconcat(OpcStr, " $dst, $b, $c"),
+                  [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
+  def _l2rus : _FL2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
+                       !strconcat(OpcStr, " $dst, $b, $c"),
+                       [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>;
+}
+
 /// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot.
 multiclass FL3R_L2RBITP<bits<9> opc1, bits<9> opc2, string OpcStr,
                         SDNode OpNode> {
@@ -294,6 +305,14 @@ multiclass FU6_LU6_np<bits<10> opc, string OpcStr> {
   def _lu6: _FLU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"), []>;
 }
 
+// Two operand short
+
+class F2R_np<bits<6> opc, string OpcStr> :
+  _F2R<opc, (outs GRRegs:$dst), (ins GRRegs:$b),
+       !strconcat(OpcStr, " $dst, $b"), []>;
+
+// Two operand long
+
 //===----------------------------------------------------------------------===//
 // Pseudo Instructions
 //===----------------------------------------------------------------------===//