[PATCH] D158931: [llvm][aarch64] Add support for the MS qualifiers __ptr32, __ptr64, __sptr, __uptr

[Aleksandr Vorobev via Phabricator via llvm-commits]

a_vorobev created this revision.
a_vorobev added reviewers: akhuang, paulwalker-arm.
a_vorobev added projects: LLVM, Backend.
Herald added subscribers: steven.zhang, hiraditya, kristof.beyls.
Herald added a project: All.
a_vorobev requested review of this revision.
Herald added a subscriber: llvm-commits.

This is backend patch for D158857 <https://reviews.llvm.org/D158857> .
This patch is 
We inject at the time of creating read , write , and cast addressspace nodes and add sign or zero extension or truncation operations to the emitted DAG nodes, depending on the type of cast. The extension itself goes like this: first we perform the same operations that we would perform when doing ptrtoint, and then we attach the required node to the resulting node as a result of this operation. This is necessary due to the fact that in the arm64 architecture there is no such thing as a 32-bit pointer, and therefore we have to ... emulate it. Additionally, instrinfo.td has been modified to have a true zero extension instead of ORRWrs, and instrinfo.cpp to provide copy operations between a 32 bit pointer register and a 64 bit output register. Also changes made to DagCombiner to handle zero extensionsion and truncation


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D158931

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  llvm/lib/Target/AArch64/AArch64.h
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/lib/Target/AArch64/AArch64TargetMachine.h
  llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
  llvm/test/CodeGen/AArch64/aarch64-mixed-ptr-sizes.ll

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