[PATCH] D158913: [RISCV] Add a cross basic block VXRM write insertion pass.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: eopXD, arcbbb, reames, kito-cheng, frasercrmck.
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This is based on D122709 <https://reviews.llvm.org/D122709> without the loop hoisting support. It has
been updated to be more consistent with the dataflow in handling in
the current vsetvli insertion pass.

I've separated VXRM handling from FRM handling since FRM requires
restoring and VXRM doesn't. We may even consider moving VXRM insertion
after register allocation to give more scheduler freedom.

A future patch will support hoisting out of loops.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D158913

Files:
  llvm/lib/Target/RISCV/CMakeLists.txt
  llvm/lib/Target/RISCV/RISCV.h
  llvm/lib/Target/RISCV/RISCVInsertReadWriteCSR.cpp
  llvm/lib/Target/RISCV/RISCVInsertWriteVXRM.cpp
  llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
  llvm/test/CodeGen/RISCV/O0-pipeline.ll
  llvm/test/CodeGen/RISCV/O3-pipeline.ll
  llvm/test/CodeGen/RISCV/rvv/vxrm-insert.ll

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