[PATCH] D158364: [DAG] SimplifyDemandedBits - if we're only demanding the signbits, a MIN/MAX node can be simplified to a OR or AND node

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon updated this revision to Diff 553432.
RKSimon retitled this revision from "[DAG] SimplifyDemandedBits - if we're only demanding the signbits, a SMIN/SMAX node can be simplified to a OR/AND node respectively." to "[DAG] SimplifyDemandedBits - if we're only demanding the signbits, a MIN/MAX node can be simplified to a OR or AND node".
RKSimon edited the summary of this revision.
RKSimon added a comment.

Added UMIN/UMAX handling and merged all MIN/MAX cases to share code

SMIN/SMAX are still missing proper known bits handling in SimplifyDemandedBits - I'll address this separately with proper test coverage.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D158364/new/

https://reviews.llvm.org/D158364

Files:
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/test/CodeGen/X86/known-signbits-vector.ll

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