[PATCH] D158830: [RISCV][MC] Allow symbol diff expression directly as LI operand

[Job Noorman via Phabricator via llvm-commits]

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D135960 <https://reviews.llvm.org/D135960> implemented support for symbol differences as an operand of LI.
However, it only worked when the symbol difference expression was first
stored in a symbol using `.set`/`.equ`. This patch makes sure the
expression can be used directly as an LI operand.

Note that when using `-filetype=asm`, the instruction printer is not
able to convert the generated ADDI back to LI, presumably because the
symbol difference expression is not recognized as an `simm12` so the
alias does not match. This means a `.s` -> `.s` round-trip produces an
ADDI instruction where there used to be an LI. Since ADDI doesn't
currently accept symbol difference expressions, the result of the
round-trip is rejected by MC.

I'm not quite sure what the best way forward is here. Is there a way to
recognize this alias without implementing support for symbol differences
for ADDI (which would be a separate patch)? Or can we just ignore this
issue for now as it seems unlikely to cause problems?

Fixes #64623


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D158830

Files:
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
  llvm/test/MC/RISCV/fixups-invalid.s
  llvm/test/MC/RISCV/rv32i-aliases-valid.s
  llvm/test/MC/RISCV/rv64i-aliases-valid.s


Index: llvm/test/MC/RISCV/rv64i-aliases-valid.s
===================================================================
--- llvm/test/MC/RISCV/rv64i-aliases-valid.s
+++ llvm/test/MC/RISCV/rv64i-aliases-valid.s
@@ -225,6 +225,11 @@
 # CHECK-OBJ-NOALIAS: addi a0, zero, 8
 li a0, CONST
 
+# CHECK-ASM: addi a0, zero, .Lbuf_end-.Lbuf
+# CHECK-ASM-NOALIAS: addi a0, zero, .Lbuf_end-.Lbuf
+# CHECK-OBJ-NOALIAS: addi a0, zero, 8
+li a0, .Lbuf_end - .Lbuf
+
 # CHECK-INST: addi a0, zero, 0
 # CHECK-ALIAS: li a0, 0
 la x10, 0
Index: llvm/test/MC/RISCV/rv32i-aliases-valid.s
===================================================================
--- llvm/test/MC/RISCV/rv32i-aliases-valid.s
+++ llvm/test/MC/RISCV/rv32i-aliases-valid.s
@@ -113,6 +113,11 @@
 # CHECK-OBJ-NOALIAS: addi a0, zero, 8
 li a0, CONST
 
+# CHECK-ASM: addi a0, zero, .Lbuf_end-.Lbuf
+# CHECK-ASM-NOALIAS: addi a0, zero, .Lbuf_end-.Lbuf
+# CHECK-OBJ-NOALIAS: addi a0, zero, 8
+li a0, .Lbuf_end - .Lbuf
+
 # CHECK-INST: addi a0, zero, 0
 # CHECK-ALIAS: li a0, 0
 la x10, 0
Index: llvm/test/MC/RISCV/fixups-invalid.s
===================================================================
--- llvm/test/MC/RISCV/fixups-invalid.s
+++ llvm/test/MC/RISCV/fixups-invalid.s
@@ -13,3 +13,5 @@
 .equ CONST, .Lbuf_end - .Lbuf
 # CHECK: error: operand must be a constant 12-bit integer
 li a0, CONST
+# CHECK: error: operand must be a constant 12-bit integer
+li a0, .Lbuf_end - .Lbuf
Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
===================================================================
--- llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
+++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
@@ -455,6 +455,11 @@
     } else if (MIFrm == RISCVII::InstFormatI) {
       FixupKind = RISCV::fixup_riscv_12_i;
     }
+  } else if (Kind == MCExpr::Binary &&
+             cast<MCBinaryExpr>(Expr)->getOpcode() == MCBinaryExpr::Sub) {
+    // Needed to support "li xi, a-b" which is translated to "addi xi, x0, a-b"
+    if (MIFrm == RISCVII::InstFormatI)
+      FixupKind = RISCV::fixup_riscv_12_i;
   }
 
   assert(FixupKind != RISCV::fixup_riscv_invalid && "Unhandled expression!");


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