[llvm] 4235bc0 - [RISCV] Fix `vmsge{u}.vx` lowering by not adding the mask operand if `vd == v0`

[via llvm-commits]

Author: imkiva
Date: 2023-08-25T13:27:16+08:00
New Revision: 4235bc0112f7714aec46cbb3c94cee57047c1abd

URL: https://github.com/llvm/llvm-project/commit/4235bc0112f7714aec46cbb3c94cee57047c1abd
DIFF: https://github.com/llvm/llvm-project/commit/4235bc0112f7714aec46cbb3c94cee57047c1abd.diff

LOG: [RISCV] Fix `vmsge{u}.vx` lowering by not adding the mask operand if `vd == v0`

According to `riscv-v-spec-1.0.pdf` page 52:

> masked va >= x, vd == v0
>   pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt
>   expansion: vmslt{u}.vx vt, va, x; vmandn.mm vd, vd, vt

The resulting `vmslt{u}.vx` is not masked. This patch fixes the logic in `RISCVAsmParser`, to make the behavior consistent with the case "masked va >= x, any vd" in the later part of the code, where no mask op is added.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D158392

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
    llvm/test/MC/RISCV/rvv/compare.s

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index ce1d3f53ffe6f7..82a483660d84bd 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -3203,7 +3203,7 @@ void RISCVAsmParser::emitVMSGE(MCInst &Inst, unsigned Opcode, SMLoc IDLoc,
                             .addOperand(Inst.getOperand(1))
                             .addOperand(Inst.getOperand(2))
                             .addOperand(Inst.getOperand(3))
-                            .addOperand(Inst.getOperand(4)));
+                            .addReg(RISCV::NoRegister));
     emitToStreamer(Out, MCInstBuilder(RISCV::VMANDN_MM)
                             .addOperand(Inst.getOperand(0))
                             .addOperand(Inst.getOperand(0))
@@ -3212,8 +3212,8 @@ void RISCVAsmParser::emitVMSGE(MCInst &Inst, unsigned Opcode, SMLoc IDLoc,
     // masked va >= x, any vd
     //
     // pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt
-    // expansion: vmslt{u}.vx vt, va, x; vmandn.mm vt, v0, vt; vmandn.mm vd,
-    // vd, v0; vmor.mm vd, vt, vd
+    // expansion: vmslt{u}.vx vt, va, x; vmandn.mm vt, v0, vt;
+    //            vmandn.mm vd, vd, v0;  vmor.mm vd, vt, vd
     assert(Inst.getOperand(1).getReg() != RISCV::V0 &&
            "The temporary vector register should not be V0.");
     emitToStreamer(Out, MCInstBuilder(Opcode)

diff  --git a/llvm/test/MC/RISCV/rvv/compare.s b/llvm/test/MC/RISCV/rvv/compare.s
index 0e724fbe9cced3..3466ee470cdbc1 100644
--- a/llvm/test/MC/RISCV/rvv/compare.s
+++ b/llvm/test/MC/RISCV/rvv/compare.s
@@ -420,21 +420,21 @@ vmsge.vx v8, v4, a0, v0.t
 # CHECK-UNKNOWN: 57 24 80 6e <unknown>
 
 vmsgeu.vx v0, v4, a0, v0.t, v2
-# CHECK-INST: vmsltu.vx v2, v4, a0, v0.t
+# CHECK-INST: vmsltu.vx v2, v4, a0
 # CHECK-INST: vmandn.mm v0, v0, v2
-# CHECK-ENCODING: [0x57,0x41,0x45,0x68]
+# CHECK-ENCODING: [0x57,0x41,0x45,0x6a]
 # CHECK-ENCODING: [0x57,0x20,0x01,0x62]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
-# CHECK-UNKNOWN: 57 41 45 68 <unknown>
+# CHECK-UNKNOWN: 57 41 45 6a <unknown>
 # CHECK-UNKNOWN: 57 20 01 62 <unknown>
 
 vmsge.vx v0, v4, a0, v0.t, v2
-# CHECK-INST: vmslt.vx v2, v4, a0, v0.t
+# CHECK-INST: vmslt.vx v2, v4, a0
 # CHECK-INST: vmandn.mm v0, v0, v2
-# CHECK-ENCODING: [0x57,0x41,0x45,0x6c]
+# CHECK-ENCODING: [0x57,0x41,0x45,0x6e]
 # CHECK-ENCODING: [0x57,0x20,0x01,0x62]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
-# CHECK-UNKNOWN: 57 41 45 6c <unknown>
+# CHECK-UNKNOWN: 57 41 45 6e <unknown>
 # CHECK-UNKNOWN: 57 20 01 62 <unknown>
 
 vmsgeu.vx v9, v4, a0, v0.t, v2