[PATCH] D158163: [RISCV] Narrow types of index operand matched pattern (shl_vl (zext_vl), C)
Liao Chunyu via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 24 21:10:40 PDT 2023
liaolucy added inline comments.
================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:11201
+bool isVMV_V_X_VLOfConstant(SDValue N, APInt &SplatVal) {
+ auto *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
+ if (C && N.getOpcode() == RISCVISD::VMV_V_X_VL) {
----------------
fakepaper56 wrote:
> fakepaper56 wrote:
> > It may cause assertion error when N has exactly one operand.
> I think you could write to
> ```
> if (N.getOpcode() == RISCVISD::VMV_V_X_VL && isa<ConstantSDNode>(N->getOperand(1))) {
> SplatVal = N->getConstantOperandVal(1);
> return true;
> }
> ```
To preserve the APInt type, I use `SplatVal = N->getConstantOperandAPInt(1)`.
Repository:
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https://reviews.llvm.org/D158163/new/
https://reviews.llvm.org/D158163
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