[llvm] 48fa79a - Revert "[DAGCombiner] Change foldAndOrOfSETCC() to optimize and/or patterns with floating points."
Konstantina Mitropoulou via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 24 20:39:34 PDT 2023
Author: Konstantina Mitropoulou
Date: 2023-08-24T20:39:04-07:00
New Revision: 48fa79a503a7cf380f98b6335fbd349afae1bd86
URL: https://github.com/llvm/llvm-project/commit/48fa79a503a7cf380f98b6335fbd349afae1bd86
DIFF: https://github.com/llvm/llvm-project/commit/48fa79a503a7cf380f98b6335fbd349afae1bd86.diff
LOG: Revert "[DAGCombiner] Change foldAndOrOfSETCC() to optimize and/or patterns with floating points."
This reverts commit 5ec13535235d07eafd64058551bc495f87c283b1.
Added:
Modified:
llvm/include/llvm/CodeGen/ISDOpcodes.h
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll
llvm/test/CodeGen/AMDGPU/fma.f16.ll
llvm/test/CodeGen/AMDGPU/or.ll
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/ISDOpcodes.h b/llvm/include/llvm/CodeGen/ISDOpcodes.h
index 15079edd3b83fc..8876a6966a58d2 100644
--- a/llvm/include/llvm/CodeGen/ISDOpcodes.h
+++ b/llvm/include/llvm/CodeGen/ISDOpcodes.h
@@ -1543,12 +1543,6 @@ inline bool isIntEqualitySetCC(CondCode Code) {
return Code == SETEQ || Code == SETNE;
}
-/// Return true if this is a setcc instruction that performs an equality
-/// comparison when used with floating point operands.
-inline bool isFPEqualitySetCC(CondCode Code) {
- return Code == SETOEQ || Code == SETONE || Code == SETUEQ || Code == SETUNE;
-}
-
/// Return true if the specified condition returns true if the two operands to
/// the condition are equal. Note that if one of the two operands is a NaN,
/// this value is meaningless.
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index b45efebe4ee4e6..b1612ae5a7f3ac 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -6042,67 +6042,6 @@ SDValue DAGCombiner::foldLogicOfSetCCs(bool IsAnd, SDValue N0, SDValue N1,
return SDValue();
}
-static bool arebothOperandsNotSNan(SDValue Operand1, SDValue Operand2,
- SelectionDAG &DAG) {
- return DAG.isKnownNeverSNaN(Operand2) && DAG.isKnownNeverSNaN(Operand1);
-}
-
-static bool arebothOperandsNotNan(SDValue Operand1, SDValue Operand2,
- SelectionDAG &DAG) {
- return DAG.isKnownNeverNaN(Operand2) && DAG.isKnownNeverNaN(Operand1);
-}
-
-static unsigned getMinMaxOpcodeForFP(SDValue Operand1, SDValue Operand2,
- ISD::CondCode CC, unsigned OrAndOpcode,
- SelectionDAG &DAG) {
- // The optimization cannot be applied for all the predicates because
- // of the way FMINNUM/FMAXNUM and FMINNUM_IEEE/FMAXNUM_IEEE handle
- // NaNs. For FMINNUM_IEEE/FMAXNUM_IEEE, the optimization cannot be
- // applied at all if one of the operands is a signaling NaN.
- const TargetLowering &TLI = DAG.getTargetLoweringInfo();
- EVT OpVT = Operand1.getValueType();
- // It is safe to use FMINNUM_IEEE/FMAXNUM_IEEE if all the operands
- // are non NaN values.
- if (((CC == ISD::SETLT || CC == ISD::SETLE) && (OrAndOpcode == ISD::OR)) ||
- ((CC == ISD::SETGT || CC == ISD::SETGE) && (OrAndOpcode == ISD::AND)))
- return arebothOperandsNotNan(Operand1, Operand2, DAG) ? ISD::FMINNUM_IEEE
- : ISD::DELETED_NODE;
- else if (((CC == ISD::SETGT || CC == ISD::SETGE) &&
- (OrAndOpcode == ISD::OR)) ||
- ((CC == ISD::SETLT || CC == ISD::SETLE) &&
- (OrAndOpcode == ISD::AND)))
- return arebothOperandsNotNan(Operand1, Operand2, DAG) ? ISD::FMAXNUM_IEEE
- : ISD::DELETED_NODE;
- // Both FMINNUM/FMAXNUM and FMINNUM_IEEE/FMAXNUM_IEEE handle quiet
- // NaNs in the same way. But, FMINNUM/FMAXNUM and FMINNUM_IEEE/
- // FMAXNUM_IEEE handle signaling NaNs
diff erently. If we cannot prove
- // that there are not any sNaNs, then the optimization is not valid
- // for FMINNUM_IEEE/FMAXNUM_IEEE. In the presence of sNaNs, we apply
- // the optimization using FMINNUM/FMAXNUM for the following cases. If
- // we can prove that we do not have any sNaNs, then we can do the
- // optimization using FMINNUM_IEEE/FMAXNUM_IEEE for the following
- // cases.
- else if (((CC == ISD::SETOLT || CC == ISD::SETOLE) &&
- (OrAndOpcode == ISD::OR)) ||
- ((CC == ISD::SETUGT || CC == ISD::SETUGE) &&
- (OrAndOpcode == ISD::AND)))
- return TLI.isOperationLegalOrCustom(ISD::FMINNUM, OpVT)
- ? ISD::FMINNUM
- : arebothOperandsNotSNan(Operand1, Operand2, DAG)
- ? ISD::FMINNUM_IEEE
- : ISD::DELETED_NODE;
- else if (((CC == ISD::SETOGT || CC == ISD::SETOGE) &&
- (OrAndOpcode == ISD::OR)) ||
- ((CC == ISD::SETULT || CC == ISD::SETULE) &&
- (OrAndOpcode == ISD::AND)))
- return TLI.isOperationLegalOrCustom(ISD::FMAXNUM, OpVT)
- ? ISD::FMAXNUM
- : arebothOperandsNotSNan(Operand1, Operand2, DAG)
- ? ISD::FMAXNUM_IEEE
- : ISD::DELETED_NODE;
- return ISD::DELETED_NODE;
-}
-
static SDValue foldAndOrOfSETCC(SDNode *LogicOp, SelectionDAG &DAG) {
using AndOrSETCCFoldKind = TargetLowering::AndOrSETCCFoldKind;
assert(
@@ -6144,20 +6083,12 @@ static SDValue foldAndOrOfSETCC(SDNode *LogicOp, SelectionDAG &DAG) {
// The optimization does not work for `==` or `!=` .
// The two comparisons should have either the same predicate or the
// predicate of one of the comparisons is the opposite of the other one.
- if (((OpVT.isInteger() && TLI.isOperationLegal(ISD::UMAX, OpVT) &&
- TLI.isOperationLegal(ISD::SMAX, OpVT) &&
- TLI.isOperationLegal(ISD::UMIN, OpVT) &&
- TLI.isOperationLegal(ISD::SMIN, OpVT)) ||
- (OpVT.isFloatingPoint() &&
- ((TLI.isOperationLegalOrCustom(ISD::FMAXNUM, OpVT) &&
- TLI.isOperationLegalOrCustom(ISD::FMINNUM, OpVT)) ||
- (TLI.isOperationLegal(ISD::FMAXNUM_IEEE, OpVT) &&
- TLI.isOperationLegal(ISD::FMINNUM_IEEE, OpVT))))) &&
- !ISD::isIntEqualitySetCC(CCL) && !ISD::isFPEqualitySetCC(CCL) &&
- CCL != ISD::SETFALSE && CCL != ISD::SETO && CCL != ISD::SETUO &&
- CCL != ISD::SETTRUE &&
- (CCL == CCR || CCL == ISD::getSetCCSwappedOperands(CCR))) {
-
+ if (OpVT.isInteger() && !ISD::isIntEqualitySetCC(CCL) &&
+ (CCL == CCR || CCL == ISD::getSetCCSwappedOperands(CCR)) &&
+ TLI.isOperationLegal(ISD::UMAX, OpVT) &&
+ TLI.isOperationLegal(ISD::SMAX, OpVT) &&
+ TLI.isOperationLegal(ISD::UMIN, OpVT) &&
+ TLI.isOperationLegal(ISD::SMIN, OpVT)) {
SDValue CommonValue, Operand1, Operand2;
ISD::CondCode CC = ISD::SETCC_INVALID;
if (CCL == CCR) {
@@ -6195,25 +6126,19 @@ static SDValue foldAndOrOfSETCC(SDNode *LogicOp, SelectionDAG &DAG) {
CC = ISD::SETCC_INVALID;
if (CC != ISD::SETCC_INVALID) {
- unsigned NewOpcode = ISD::DELETED_NODE;
+ unsigned NewOpcode;
bool IsSigned = isSignedIntSetCC(CC);
- if (OpVT.isInteger()) {
- bool IsLess = (CC == ISD::SETLE || CC == ISD::SETULE ||
- CC == ISD::SETLT || CC == ISD::SETULT);
- bool IsOr = (LogicOp->getOpcode() == ISD::OR);
- if (IsLess == IsOr)
- NewOpcode = IsSigned ? ISD::SMIN : ISD::UMIN;
- else
- NewOpcode = IsSigned ? ISD::SMAX : ISD::UMAX;
- } else if (OpVT.isFloatingPoint())
- NewOpcode = getMinMaxOpcodeForFP(Operand1, Operand2, CC,
- LogicOp->getOpcode(), DAG);
-
- if (NewOpcode != ISD::DELETED_NODE) {
- SDValue MinMaxValue =
- DAG.getNode(NewOpcode, DL, OpVT, Operand1, Operand2);
- return DAG.getSetCC(DL, VT, MinMaxValue, CommonValue, CC);
- }
+ bool IsLess = (CC == ISD::SETLE || CC == ISD::SETULE ||
+ CC == ISD::SETLT || CC == ISD::SETULT);
+ bool IsOr = (LogicOp->getOpcode() == ISD::OR);
+ if (IsLess == IsOr)
+ NewOpcode = IsSigned ? ISD::SMIN : ISD::UMIN;
+ else
+ NewOpcode = IsSigned ? ISD::SMAX : ISD::UMAX;
+
+ SDValue MinMaxValue =
+ DAG.getNode(NewOpcode, DL, OpVT, Operand1, Operand2);
+ return DAG.getSetCC(DL, VT, MinMaxValue, CommonValue, CC);
}
}
diff --git a/llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll b/llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll
index 6efbd6ce87385e..0926a2295f0a57 100644
--- a/llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll
+++ b/llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll
@@ -1,19 +1,18 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
-; RUN: llc -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs -amdgpu-enable-delay-alu=0 < %s | FileCheck %s -check-prefixes=GCN,GFX11
-; RUN: llc -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs -amdgpu-enable-delay-alu=0 -enable-no-nans-fp-math < %s | FileCheck %s -check-prefixes=GCN,GFX11NONANS
+; RUN: llc -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs -amdgpu-enable-delay-alu=0 < %s | FileCheck %s
; The tests check the following optimization of DAGCombiner:
; CMP(A,C)||CMP(B,C) => CMP(MIN/MAX(A,B), C)
; CMP(A,C)&&CMP(B,C) => CMP(MIN/MAX(A,B), C)
define i1 @test1(i32 %arg1, i32 %arg2) {
-; GCN-LABEL: test1:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_min_i32_e32 v0, v0, v1
-; GCN-NEXT: v_cmp_gt_i32_e32 vcc_lo, 0x3e8, v0
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test1:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_min_i32_e32 v0, v0, v1
+; CHECK-NEXT: v_cmp_gt_i32_e32 vcc_lo, 0x3e8, v0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp slt i32 %arg1, 1000
%cmp2 = icmp slt i32 %arg2, 1000
%or = or i1 %cmp1, %cmp2
@@ -21,13 +20,13 @@ define i1 @test1(i32 %arg1, i32 %arg2) {
}
define i1 @test2(i32 %arg1, i32 %arg2) {
-; GCN-LABEL: test2:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_min_u32_e32 v0, v0, v1
-; GCN-NEXT: v_cmp_gt_u32_e32 vcc_lo, 0x3e8, v0
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test2:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_min_u32_e32 v0, v0, v1
+; CHECK-NEXT: v_cmp_gt_u32_e32 vcc_lo, 0x3e8, v0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp ult i32 %arg1, 1000
%cmp2 = icmp ult i32 %arg2, 1000
%or = or i1 %cmp1, %cmp2
@@ -35,13 +34,13 @@ define i1 @test2(i32 %arg1, i32 %arg2) {
}
define i1 @test3(i32 %arg1, i32 %arg2) {
-; GCN-LABEL: test3:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_min_i32_e32 v0, v0, v1
-; GCN-NEXT: v_cmp_gt_i32_e32 vcc_lo, 0x3e9, v0
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test3:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_min_i32_e32 v0, v0, v1
+; CHECK-NEXT: v_cmp_gt_i32_e32 vcc_lo, 0x3e9, v0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp sle i32 %arg1, 1000
%cmp2 = icmp sle i32 %arg2, 1000
%or = or i1 %cmp1, %cmp2
@@ -49,13 +48,13 @@ define i1 @test3(i32 %arg1, i32 %arg2) {
}
define i1 @test4(i32 %arg1, i32 %arg2) {
-; GCN-LABEL: test4:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_min_u32_e32 v0, v0, v1
-; GCN-NEXT: v_cmp_gt_u32_e32 vcc_lo, 0x3e9, v0
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test4:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_min_u32_e32 v0, v0, v1
+; CHECK-NEXT: v_cmp_gt_u32_e32 vcc_lo, 0x3e9, v0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp ule i32 %arg1, 1000
%cmp2 = icmp ule i32 %arg2, 1000
%or = or i1 %cmp1, %cmp2
@@ -63,13 +62,13 @@ define i1 @test4(i32 %arg1, i32 %arg2) {
}
define i1 @test5(i32 %arg1, i32 %arg2) {
-; GCN-LABEL: test5:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_max_i32_e32 v0, v0, v1
-; GCN-NEXT: v_cmp_lt_i32_e32 vcc_lo, 0x3e8, v0
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test5:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_max_i32_e32 v0, v0, v1
+; CHECK-NEXT: v_cmp_lt_i32_e32 vcc_lo, 0x3e8, v0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp sgt i32 %arg1, 1000
%cmp2 = icmp sgt i32 %arg2, 1000
%or = or i1 %cmp1, %cmp2
@@ -77,13 +76,13 @@ define i1 @test5(i32 %arg1, i32 %arg2) {
}
define i1 @test6(i32 %arg1, i32 %arg2) {
-; GCN-LABEL: test6:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_max_u32_e32 v0, v0, v1
-; GCN-NEXT: v_cmp_lt_u32_e32 vcc_lo, 0x3e8, v0
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test6:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_max_u32_e32 v0, v0, v1
+; CHECK-NEXT: v_cmp_lt_u32_e32 vcc_lo, 0x3e8, v0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp ugt i32 %arg1, 1000
%cmp2 = icmp ugt i32 %arg2, 1000
%or = or i1 %cmp1, %cmp2
@@ -91,13 +90,13 @@ define i1 @test6(i32 %arg1, i32 %arg2) {
}
define i1 @test7(i32 %arg1, i32 %arg2) {
-; GCN-LABEL: test7:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_max_i32_e32 v0, v0, v1
-; GCN-NEXT: v_cmp_lt_i32_e32 vcc_lo, 0x3e7, v0
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test7:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_max_i32_e32 v0, v0, v1
+; CHECK-NEXT: v_cmp_lt_i32_e32 vcc_lo, 0x3e7, v0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp sge i32 %arg1, 1000
%cmp2 = icmp sge i32 %arg2, 1000
%or = or i1 %cmp1, %cmp2
@@ -105,13 +104,13 @@ define i1 @test7(i32 %arg1, i32 %arg2) {
}
define i1 @test8(i32 %arg1, i32 %arg2) {
-; GCN-LABEL: test8:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_max_u32_e32 v0, v0, v1
-; GCN-NEXT: v_cmp_lt_u32_e32 vcc_lo, 0x3e7, v0
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test8:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_max_u32_e32 v0, v0, v1
+; CHECK-NEXT: v_cmp_lt_u32_e32 vcc_lo, 0x3e7, v0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp uge i32 %arg1, 1000
%cmp2 = icmp uge i32 %arg2, 1000
%or = or i1 %cmp1, %cmp2
@@ -119,13 +118,13 @@ define i1 @test8(i32 %arg1, i32 %arg2) {
}
define i1 @test9(i32 %arg1, i32 %arg2, i32 %arg3) {
-; GCN-LABEL: test9:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_min_i32_e32 v0, v0, v1
-; GCN-NEXT: v_cmp_lt_i32_e32 vcc_lo, v0, v2
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test9:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_min_i32_e32 v0, v0, v1
+; CHECK-NEXT: v_cmp_lt_i32_e32 vcc_lo, v0, v2
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp slt i32 %arg1, %arg3
%cmp2 = icmp slt i32 %arg2, %arg3
%or = or i1 %cmp1, %cmp2
@@ -133,13 +132,13 @@ define i1 @test9(i32 %arg1, i32 %arg2, i32 %arg3) {
}
define i1 @test10(i32 %arg1, i32 %arg2, i32 %arg3) {
-; GCN-LABEL: test10:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_min_u32_e32 v0, v0, v1
-; GCN-NEXT: v_cmp_lt_u32_e32 vcc_lo, v0, v2
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test10:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_min_u32_e32 v0, v0, v1
+; CHECK-NEXT: v_cmp_lt_u32_e32 vcc_lo, v0, v2
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp ult i32 %arg1, %arg3
%cmp2 = icmp ult i32 %arg2, %arg3
%or = or i1 %cmp1, %cmp2
@@ -147,13 +146,13 @@ define i1 @test10(i32 %arg1, i32 %arg2, i32 %arg3) {
}
define i1 @test11(i32 %arg1, i32 %arg2, i32 %arg3) {
-; GCN-LABEL: test11:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_min_i32_e32 v0, v0, v1
-; GCN-NEXT: v_cmp_le_i32_e32 vcc_lo, v0, v2
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test11:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_min_i32_e32 v0, v0, v1
+; CHECK-NEXT: v_cmp_le_i32_e32 vcc_lo, v0, v2
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp sle i32 %arg1, %arg3
%cmp2 = icmp sle i32 %arg2, %arg3
%or = or i1 %cmp1, %cmp2
@@ -161,13 +160,13 @@ define i1 @test11(i32 %arg1, i32 %arg2, i32 %arg3) {
}
define i1 @test12(i32 %arg1, i32 %arg2, i32 %arg3) {
-; GCN-LABEL: test12:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_min_u32_e32 v0, v0, v1
-; GCN-NEXT: v_cmp_le_u32_e32 vcc_lo, v0, v2
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test12:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_min_u32_e32 v0, v0, v1
+; CHECK-NEXT: v_cmp_le_u32_e32 vcc_lo, v0, v2
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp ule i32 %arg1, %arg3
%cmp2 = icmp ule i32 %arg2, %arg3
%or = or i1 %cmp1, %cmp2
@@ -175,13 +174,13 @@ define i1 @test12(i32 %arg1, i32 %arg2, i32 %arg3) {
}
define i1 @test13(i32 %arg1, i32 %arg2, i32 %arg3) {
-; GCN-LABEL: test13:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_max_i32_e32 v0, v0, v1
-; GCN-NEXT: v_cmp_gt_i32_e32 vcc_lo, v0, v2
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test13:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_max_i32_e32 v0, v0, v1
+; CHECK-NEXT: v_cmp_gt_i32_e32 vcc_lo, v0, v2
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp sgt i32 %arg1, %arg3
%cmp2 = icmp sgt i32 %arg2, %arg3
%or = or i1 %cmp1, %cmp2
@@ -189,13 +188,13 @@ define i1 @test13(i32 %arg1, i32 %arg2, i32 %arg3) {
}
define i1 @test14(i32 %arg1, i32 %arg2, i32 %arg3) {
-; GCN-LABEL: test14:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_max_u32_e32 v0, v0, v1
-; GCN-NEXT: v_cmp_gt_u32_e32 vcc_lo, v0, v2
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test14:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_max_u32_e32 v0, v0, v1
+; CHECK-NEXT: v_cmp_gt_u32_e32 vcc_lo, v0, v2
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp ugt i32 %arg1, %arg3
%cmp2 = icmp ugt i32 %arg2, %arg3
%or = or i1 %cmp1, %cmp2
@@ -203,13 +202,13 @@ define i1 @test14(i32 %arg1, i32 %arg2, i32 %arg3) {
}
define i1 @test15(i32 %arg1, i32 %arg2, i32 %arg3) {
-; GCN-LABEL: test15:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_max_i32_e32 v0, v0, v1
-; GCN-NEXT: v_cmp_ge_i32_e32 vcc_lo, v0, v2
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test15:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_max_i32_e32 v0, v0, v1
+; CHECK-NEXT: v_cmp_ge_i32_e32 vcc_lo, v0, v2
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp sge i32 %arg1, %arg3
%cmp2 = icmp sge i32 %arg2, %arg3
%or = or i1 %cmp1, %cmp2
@@ -217,13 +216,13 @@ define i1 @test15(i32 %arg1, i32 %arg2, i32 %arg3) {
}
define i1 @test16(i32 %arg1, i32 %arg2, i32 %arg3) {
-; GCN-LABEL: test16:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_max_u32_e32 v0, v0, v1
-; GCN-NEXT: v_cmp_ge_u32_e32 vcc_lo, v0, v2
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test16:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_max_u32_e32 v0, v0, v1
+; CHECK-NEXT: v_cmp_ge_u32_e32 vcc_lo, v0, v2
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp uge i32 %arg1, %arg3
%cmp2 = icmp uge i32 %arg2, %arg3
%or = or i1 %cmp1, %cmp2
@@ -231,13 +230,13 @@ define i1 @test16(i32 %arg1, i32 %arg2, i32 %arg3) {
}
define i1 @test17(i32 %arg1, i32 %arg2) {
-; GCN-LABEL: test17:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_max_i32_e32 v0, v0, v1
-; GCN-NEXT: v_cmp_gt_i32_e32 vcc_lo, 0x3e8, v0
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test17:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_max_i32_e32 v0, v0, v1
+; CHECK-NEXT: v_cmp_gt_i32_e32 vcc_lo, 0x3e8, v0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp slt i32 %arg1, 1000
%cmp2 = icmp slt i32 %arg2, 1000
%and = and i1 %cmp1, %cmp2
@@ -245,13 +244,13 @@ define i1 @test17(i32 %arg1, i32 %arg2) {
}
define i1 @test18(i32 %arg1, i32 %arg2) {
-; GCN-LABEL: test18:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_max_u32_e32 v0, v0, v1
-; GCN-NEXT: v_cmp_gt_u32_e32 vcc_lo, 0x3e8, v0
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test18:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_max_u32_e32 v0, v0, v1
+; CHECK-NEXT: v_cmp_gt_u32_e32 vcc_lo, 0x3e8, v0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp ult i32 %arg1, 1000
%cmp2 = icmp ult i32 %arg2, 1000
%and = and i1 %cmp1, %cmp2
@@ -259,13 +258,13 @@ define i1 @test18(i32 %arg1, i32 %arg2) {
}
define i1 @test19(i32 %arg1, i32 %arg2) {
-; GCN-LABEL: test19:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_max_i32_e32 v0, v0, v1
-; GCN-NEXT: v_cmp_gt_i32_e32 vcc_lo, 0x3e9, v0
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test19:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_max_i32_e32 v0, v0, v1
+; CHECK-NEXT: v_cmp_gt_i32_e32 vcc_lo, 0x3e9, v0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp sle i32 %arg1, 1000
%cmp2 = icmp sle i32 %arg2, 1000
%and = and i1 %cmp1, %cmp2
@@ -273,13 +272,13 @@ define i1 @test19(i32 %arg1, i32 %arg2) {
}
define i1 @test20(i32 %arg1, i32 %arg2) {
-; GCN-LABEL: test20:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_max_u32_e32 v0, v0, v1
-; GCN-NEXT: v_cmp_gt_u32_e32 vcc_lo, 0x3e9, v0
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test20:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_max_u32_e32 v0, v0, v1
+; CHECK-NEXT: v_cmp_gt_u32_e32 vcc_lo, 0x3e9, v0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp ule i32 %arg1, 1000
%cmp2 = icmp ule i32 %arg2, 1000
%and = and i1 %cmp1, %cmp2
@@ -287,13 +286,13 @@ define i1 @test20(i32 %arg1, i32 %arg2) {
}
define i1 @test21(i32 %arg1, i32 %arg2) {
-; GCN-LABEL: test21:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_min_i32_e32 v0, v0, v1
-; GCN-NEXT: v_cmp_lt_i32_e32 vcc_lo, 0x3e8, v0
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test21:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_min_i32_e32 v0, v0, v1
+; CHECK-NEXT: v_cmp_lt_i32_e32 vcc_lo, 0x3e8, v0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp sgt i32 %arg1, 1000
%cmp2 = icmp sgt i32 %arg2, 1000
%and = and i1 %cmp1, %cmp2
@@ -301,13 +300,13 @@ define i1 @test21(i32 %arg1, i32 %arg2) {
}
define i1 @test22(i32 %arg1, i32 %arg2) {
-; GCN-LABEL: test22:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_min_u32_e32 v0, v0, v1
-; GCN-NEXT: v_cmp_lt_u32_e32 vcc_lo, 0x3e8, v0
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test22:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_min_u32_e32 v0, v0, v1
+; CHECK-NEXT: v_cmp_lt_u32_e32 vcc_lo, 0x3e8, v0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp ugt i32 %arg1, 1000
%cmp2 = icmp ugt i32 %arg2, 1000
%and = and i1 %cmp1, %cmp2
@@ -315,13 +314,13 @@ define i1 @test22(i32 %arg1, i32 %arg2) {
}
define i1 @test23(i32 %arg1, i32 %arg2) {
-; GCN-LABEL: test23:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_min_i32_e32 v0, v0, v1
-; GCN-NEXT: v_cmp_lt_i32_e32 vcc_lo, 0x3e7, v0
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test23:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_min_i32_e32 v0, v0, v1
+; CHECK-NEXT: v_cmp_lt_i32_e32 vcc_lo, 0x3e7, v0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp sge i32 %arg1, 1000
%cmp2 = icmp sge i32 %arg2, 1000
%and = and i1 %cmp1, %cmp2
@@ -329,13 +328,13 @@ define i1 @test23(i32 %arg1, i32 %arg2) {
}
define i1 @test24(i32 %arg1, i32 %arg2) {
-; GCN-LABEL: test24:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_min_u32_e32 v0, v0, v1
-; GCN-NEXT: v_cmp_lt_u32_e32 vcc_lo, 0x3e7, v0
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test24:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_min_u32_e32 v0, v0, v1
+; CHECK-NEXT: v_cmp_lt_u32_e32 vcc_lo, 0x3e7, v0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp uge i32 %arg1, 1000
%cmp2 = icmp uge i32 %arg2, 1000
%and = and i1 %cmp1, %cmp2
@@ -343,13 +342,13 @@ define i1 @test24(i32 %arg1, i32 %arg2) {
}
define i1 @test25(i32 %arg1, i32 %arg2, i32 %arg3) {
-; GCN-LABEL: test25:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_max_i32_e32 v0, v0, v1
-; GCN-NEXT: v_cmp_lt_i32_e32 vcc_lo, v0, v2
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test25:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_max_i32_e32 v0, v0, v1
+; CHECK-NEXT: v_cmp_lt_i32_e32 vcc_lo, v0, v2
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp slt i32 %arg1, %arg3
%cmp2 = icmp slt i32 %arg2, %arg3
%and = and i1 %cmp1, %cmp2
@@ -357,13 +356,13 @@ define i1 @test25(i32 %arg1, i32 %arg2, i32 %arg3) {
}
define i1 @test26(i32 %arg1, i32 %arg2, i32 %arg3) {
-; GCN-LABEL: test26:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_max_u32_e32 v0, v0, v1
-; GCN-NEXT: v_cmp_lt_u32_e32 vcc_lo, v0, v2
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test26:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_max_u32_e32 v0, v0, v1
+; CHECK-NEXT: v_cmp_lt_u32_e32 vcc_lo, v0, v2
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp ult i32 %arg1, %arg3
%cmp2 = icmp ult i32 %arg2, %arg3
%and = and i1 %cmp1, %cmp2
@@ -371,13 +370,13 @@ define i1 @test26(i32 %arg1, i32 %arg2, i32 %arg3) {
}
define i1 @test27(i32 %arg1, i32 %arg2, i32 %arg3) {
-; GCN-LABEL: test27:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_max_i32_e32 v0, v0, v1
-; GCN-NEXT: v_cmp_le_i32_e32 vcc_lo, v0, v2
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test27:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_max_i32_e32 v0, v0, v1
+; CHECK-NEXT: v_cmp_le_i32_e32 vcc_lo, v0, v2
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp sle i32 %arg1, %arg3
%cmp2 = icmp sle i32 %arg2, %arg3
%and = and i1 %cmp1, %cmp2
@@ -385,13 +384,13 @@ define i1 @test27(i32 %arg1, i32 %arg2, i32 %arg3) {
}
define i1 @test28(i32 %arg1, i32 %arg2, i32 %arg3) {
-; GCN-LABEL: test28:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_max_u32_e32 v0, v0, v1
-; GCN-NEXT: v_cmp_le_u32_e32 vcc_lo, v0, v2
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test28:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_max_u32_e32 v0, v0, v1
+; CHECK-NEXT: v_cmp_le_u32_e32 vcc_lo, v0, v2
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp ule i32 %arg1, %arg3
%cmp2 = icmp ule i32 %arg2, %arg3
%and = and i1 %cmp1, %cmp2
@@ -399,13 +398,13 @@ define i1 @test28(i32 %arg1, i32 %arg2, i32 %arg3) {
}
define i1 @test29(i32 %arg1, i32 %arg2, i32 %arg3) {
-; GCN-LABEL: test29:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_min_i32_e32 v0, v0, v1
-; GCN-NEXT: v_cmp_gt_i32_e32 vcc_lo, v0, v2
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test29:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_min_i32_e32 v0, v0, v1
+; CHECK-NEXT: v_cmp_gt_i32_e32 vcc_lo, v0, v2
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp sgt i32 %arg1, %arg3
%cmp2 = icmp sgt i32 %arg2, %arg3
%and = and i1 %cmp1, %cmp2
@@ -413,13 +412,13 @@ define i1 @test29(i32 %arg1, i32 %arg2, i32 %arg3) {
}
define i1 @test30(i32 %arg1, i32 %arg2, i32 %arg3) {
-; GCN-LABEL: test30:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_min_u32_e32 v0, v0, v1
-; GCN-NEXT: v_cmp_gt_u32_e32 vcc_lo, v0, v2
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test30:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_min_u32_e32 v0, v0, v1
+; CHECK-NEXT: v_cmp_gt_u32_e32 vcc_lo, v0, v2
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp ugt i32 %arg1, %arg3
%cmp2 = icmp ugt i32 %arg2, %arg3
%and = and i1 %cmp1, %cmp2
@@ -427,13 +426,13 @@ define i1 @test30(i32 %arg1, i32 %arg2, i32 %arg3) {
}
define i1 @test31(i32 %arg1, i32 %arg2, i32 %arg3) {
-; GCN-LABEL: test31:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_min_i32_e32 v0, v0, v1
-; GCN-NEXT: v_cmp_ge_i32_e32 vcc_lo, v0, v2
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test31:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_min_i32_e32 v0, v0, v1
+; CHECK-NEXT: v_cmp_ge_i32_e32 vcc_lo, v0, v2
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp sge i32 %arg1, %arg3
%cmp2 = icmp sge i32 %arg2, %arg3
%and = and i1 %cmp1, %cmp2
@@ -441,13 +440,13 @@ define i1 @test31(i32 %arg1, i32 %arg2, i32 %arg3) {
}
define i1 @test32(i32 %arg1, i32 %arg2, i32 %arg3) {
-; GCN-LABEL: test32:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_min_u32_e32 v0, v0, v1
-; GCN-NEXT: v_cmp_ge_u32_e32 vcc_lo, v0, v2
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test32:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_min_u32_e32 v0, v0, v1
+; CHECK-NEXT: v_cmp_ge_u32_e32 vcc_lo, v0, v2
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp uge i32 %arg1, %arg3
%cmp2 = icmp uge i32 %arg2, %arg3
%and = and i1 %cmp1, %cmp2
@@ -455,13 +454,13 @@ define i1 @test32(i32 %arg1, i32 %arg2, i32 %arg3) {
}
define i1 @test33(i32 %arg1, i32 %arg2) {
-; GCN-LABEL: test33:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_max_i32_e32 v1, 0x3e8, v1
-; GCN-NEXT: v_cmp_gt_i32_e32 vcc_lo, v1, v0
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test33:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_max_i32_e32 v1, 0x3e8, v1
+; CHECK-NEXT: v_cmp_gt_i32_e32 vcc_lo, v1, v0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp slt i32 %arg1, %arg2
%cmp2 = icmp slt i32 %arg1, 1000
%or = or i1 %cmp1, %cmp2
@@ -469,18 +468,18 @@ define i1 @test33(i32 %arg1, i32 %arg2) {
}
define amdgpu_gfx void @test34(i32 inreg %arg1, i32 inreg %arg2) {
-; GCN-LABEL: test34:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: s_min_i32 s0, s4, s5
-; GCN-NEXT: v_mov_b32_e32 v0, 0
-; GCN-NEXT: s_cmpk_lt_i32 s0, 0x3e9
-; GCN-NEXT: v_mov_b32_e32 v1, 0
-; GCN-NEXT: s_cselect_b32 s0, -1, 0
-; GCN-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
-; GCN-NEXT: global_store_b8 v[0:1], v2, off dlc
-; GCN-NEXT: s_waitcnt_vscnt null, 0x0
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test34:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: s_min_i32 s0, s4, s5
+; CHECK-NEXT: v_mov_b32_e32 v0, 0
+; CHECK-NEXT: s_cmpk_lt_i32 s0, 0x3e9
+; CHECK-NEXT: v_mov_b32_e32 v1, 0
+; CHECK-NEXT: s_cselect_b32 s0, -1, 0
+; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
+; CHECK-NEXT: global_store_b8 v[0:1], v2, off dlc
+; CHECK-NEXT: s_waitcnt_vscnt null, 0x0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp sle i32 %arg1, 1000
%cmp2 = icmp sle i32 %arg2, 1000
%or = or i1 %cmp1, %cmp2
@@ -489,18 +488,18 @@ define amdgpu_gfx void @test34(i32 inreg %arg1, i32 inreg %arg2) {
}
define amdgpu_gfx void @test35(i32 inreg %arg1, i32 inreg %arg2) {
-; GCN-LABEL: test35:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: s_max_i32 s0, s4, s5
-; GCN-NEXT: v_mov_b32_e32 v0, 0
-; GCN-NEXT: s_cmpk_gt_i32 s0, 0x3e8
-; GCN-NEXT: v_mov_b32_e32 v1, 0
-; GCN-NEXT: s_cselect_b32 s0, -1, 0
-; GCN-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
-; GCN-NEXT: global_store_b8 v[0:1], v2, off dlc
-; GCN-NEXT: s_waitcnt_vscnt null, 0x0
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test35:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: s_max_i32 s0, s4, s5
+; CHECK-NEXT: v_mov_b32_e32 v0, 0
+; CHECK-NEXT: s_cmpk_gt_i32 s0, 0x3e8
+; CHECK-NEXT: v_mov_b32_e32 v1, 0
+; CHECK-NEXT: s_cselect_b32 s0, -1, 0
+; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
+; CHECK-NEXT: global_store_b8 v[0:1], v2, off dlc
+; CHECK-NEXT: s_waitcnt_vscnt null, 0x0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp sgt i32 %arg1, 1000
%cmp2 = icmp sgt i32 %arg2, 1000
%or = or i1 %cmp1, %cmp2
@@ -509,18 +508,18 @@ define amdgpu_gfx void @test35(i32 inreg %arg1, i32 inreg %arg2) {
}
define amdgpu_gfx void @test36(i32 inreg %arg1, i32 inreg %arg2, i32 inreg %arg3) {
-; GCN-LABEL: test36:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: s_min_u32 s0, s4, s5
-; GCN-NEXT: v_mov_b32_e32 v0, 0
-; GCN-NEXT: s_cmp_lt_u32 s0, s6
-; GCN-NEXT: v_mov_b32_e32 v1, 0
-; GCN-NEXT: s_cselect_b32 s0, -1, 0
-; GCN-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
-; GCN-NEXT: global_store_b8 v[0:1], v2, off dlc
-; GCN-NEXT: s_waitcnt_vscnt null, 0x0
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test36:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: s_min_u32 s0, s4, s5
+; CHECK-NEXT: v_mov_b32_e32 v0, 0
+; CHECK-NEXT: s_cmp_lt_u32 s0, s6
+; CHECK-NEXT: v_mov_b32_e32 v1, 0
+; CHECK-NEXT: s_cselect_b32 s0, -1, 0
+; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
+; CHECK-NEXT: global_store_b8 v[0:1], v2, off dlc
+; CHECK-NEXT: s_waitcnt_vscnt null, 0x0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp ult i32 %arg1, %arg3
%cmp2 = icmp ult i32 %arg2, %arg3
%or = or i1 %cmp1, %cmp2
@@ -529,18 +528,18 @@ define amdgpu_gfx void @test36(i32 inreg %arg1, i32 inreg %arg2, i32 inreg %arg3
}
define amdgpu_gfx void @test37(i32 inreg %arg1, i32 inreg %arg2, i32 inreg %arg3) {
-; GCN-LABEL: test37:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: s_max_i32 s0, s4, s5
-; GCN-NEXT: v_mov_b32_e32 v0, 0
-; GCN-NEXT: s_cmp_ge_i32 s0, s6
-; GCN-NEXT: v_mov_b32_e32 v1, 0
-; GCN-NEXT: s_cselect_b32 s0, -1, 0
-; GCN-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
-; GCN-NEXT: global_store_b8 v[0:1], v2, off dlc
-; GCN-NEXT: s_waitcnt_vscnt null, 0x0
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test37:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: s_max_i32 s0, s4, s5
+; CHECK-NEXT: v_mov_b32_e32 v0, 0
+; CHECK-NEXT: s_cmp_ge_i32 s0, s6
+; CHECK-NEXT: v_mov_b32_e32 v1, 0
+; CHECK-NEXT: s_cselect_b32 s0, -1, 0
+; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
+; CHECK-NEXT: global_store_b8 v[0:1], v2, off dlc
+; CHECK-NEXT: s_waitcnt_vscnt null, 0x0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp sge i32 %arg1, %arg3
%cmp2 = icmp sge i32 %arg2, %arg3
%or = or i1 %cmp1, %cmp2
@@ -549,18 +548,18 @@ define amdgpu_gfx void @test37(i32 inreg %arg1, i32 inreg %arg2, i32 inreg %arg3
}
define amdgpu_gfx void @test38(i32 inreg %arg1, i32 inreg %arg2) {
-; GCN-LABEL: test38:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: s_max_u32 s0, s4, s5
-; GCN-NEXT: v_mov_b32_e32 v0, 0
-; GCN-NEXT: s_cmpk_lt_u32 s0, 0x3e9
-; GCN-NEXT: v_mov_b32_e32 v1, 0
-; GCN-NEXT: s_cselect_b32 s0, -1, 0
-; GCN-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
-; GCN-NEXT: global_store_b8 v[0:1], v2, off dlc
-; GCN-NEXT: s_waitcnt_vscnt null, 0x0
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test38:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: s_max_u32 s0, s4, s5
+; CHECK-NEXT: v_mov_b32_e32 v0, 0
+; CHECK-NEXT: s_cmpk_lt_u32 s0, 0x3e9
+; CHECK-NEXT: v_mov_b32_e32 v1, 0
+; CHECK-NEXT: s_cselect_b32 s0, -1, 0
+; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
+; CHECK-NEXT: global_store_b8 v[0:1], v2, off dlc
+; CHECK-NEXT: s_waitcnt_vscnt null, 0x0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp ule i32 %arg1, 1000
%cmp2 = icmp ule i32 %arg2, 1000
%and = and i1 %cmp1, %cmp2
@@ -569,18 +568,18 @@ define amdgpu_gfx void @test38(i32 inreg %arg1, i32 inreg %arg2) {
}
define amdgpu_gfx void @test39(i32 inreg %arg1, i32 inreg %arg2) {
-; GCN-LABEL: test39:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: s_min_i32 s0, s4, s5
-; GCN-NEXT: v_mov_b32_e32 v0, 0
-; GCN-NEXT: s_cmpk_gt_i32 s0, 0x3e7
-; GCN-NEXT: v_mov_b32_e32 v1, 0
-; GCN-NEXT: s_cselect_b32 s0, -1, 0
-; GCN-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
-; GCN-NEXT: global_store_b8 v[0:1], v2, off dlc
-; GCN-NEXT: s_waitcnt_vscnt null, 0x0
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test39:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: s_min_i32 s0, s4, s5
+; CHECK-NEXT: v_mov_b32_e32 v0, 0
+; CHECK-NEXT: s_cmpk_gt_i32 s0, 0x3e7
+; CHECK-NEXT: v_mov_b32_e32 v1, 0
+; CHECK-NEXT: s_cselect_b32 s0, -1, 0
+; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
+; CHECK-NEXT: global_store_b8 v[0:1], v2, off dlc
+; CHECK-NEXT: s_waitcnt_vscnt null, 0x0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp sge i32 %arg1, 1000
%cmp2 = icmp sge i32 %arg2, 1000
%and = and i1 %cmp1, %cmp2
@@ -589,18 +588,18 @@ define amdgpu_gfx void @test39(i32 inreg %arg1, i32 inreg %arg2) {
}
define amdgpu_gfx void @test40(i32 inreg %arg1, i32 inreg %arg2, i32 inreg %arg3) {
-; GCN-LABEL: test40:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: s_max_i32 s0, s4, s5
-; GCN-NEXT: v_mov_b32_e32 v0, 0
-; GCN-NEXT: s_cmp_le_i32 s0, s6
-; GCN-NEXT: v_mov_b32_e32 v1, 0
-; GCN-NEXT: s_cselect_b32 s0, -1, 0
-; GCN-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
-; GCN-NEXT: global_store_b8 v[0:1], v2, off dlc
-; GCN-NEXT: s_waitcnt_vscnt null, 0x0
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test40:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: s_max_i32 s0, s4, s5
+; CHECK-NEXT: v_mov_b32_e32 v0, 0
+; CHECK-NEXT: s_cmp_le_i32 s0, s6
+; CHECK-NEXT: v_mov_b32_e32 v1, 0
+; CHECK-NEXT: s_cselect_b32 s0, -1, 0
+; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
+; CHECK-NEXT: global_store_b8 v[0:1], v2, off dlc
+; CHECK-NEXT: s_waitcnt_vscnt null, 0x0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp sle i32 %arg1, %arg3
%cmp2 = icmp sle i32 %arg2, %arg3
%and = and i1 %cmp1, %cmp2
@@ -609,18 +608,18 @@ define amdgpu_gfx void @test40(i32 inreg %arg1, i32 inreg %arg2, i32 inreg %arg3
}
define amdgpu_gfx void @test41(i32 inreg %arg1, i32 inreg %arg2, i32 inreg %arg3) {
-; GCN-LABEL: test41:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: s_min_u32 s0, s4, s5
-; GCN-NEXT: v_mov_b32_e32 v0, 0
-; GCN-NEXT: s_cmp_ge_u32 s0, s6
-; GCN-NEXT: v_mov_b32_e32 v1, 0
-; GCN-NEXT: s_cselect_b32 s0, -1, 0
-; GCN-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
-; GCN-NEXT: global_store_b8 v[0:1], v2, off dlc
-; GCN-NEXT: s_waitcnt_vscnt null, 0x0
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test41:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: s_min_u32 s0, s4, s5
+; CHECK-NEXT: v_mov_b32_e32 v0, 0
+; CHECK-NEXT: s_cmp_ge_u32 s0, s6
+; CHECK-NEXT: v_mov_b32_e32 v1, 0
+; CHECK-NEXT: s_cselect_b32 s0, -1, 0
+; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
+; CHECK-NEXT: global_store_b8 v[0:1], v2, off dlc
+; CHECK-NEXT: s_waitcnt_vscnt null, 0x0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp uge i32 %arg1, %arg3
%cmp2 = icmp uge i32 %arg2, %arg3
%and = and i1 %cmp1, %cmp2
@@ -629,13 +628,13 @@ define amdgpu_gfx void @test41(i32 inreg %arg1, i32 inreg %arg2, i32 inreg %arg3
}
define i1 @test42(i32 %arg1, i32 %arg2, i32 %arg3) {
-; GCN-LABEL: test42:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_min_u32_e32 v0, v0, v1
-; GCN-NEXT: v_cmp_gt_u32_e32 vcc_lo, v0, v2
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test42:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_min_u32_e32 v0, v0, v1
+; CHECK-NEXT: v_cmp_gt_u32_e32 vcc_lo, v0, v2
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp ult i32 %arg3, %arg1
%cmp2 = icmp ult i32 %arg3, %arg2
%or = and i1 %cmp1, %cmp2
@@ -643,13 +642,13 @@ define i1 @test42(i32 %arg1, i32 %arg2, i32 %arg3) {
}
define i1 @test43(i32 %arg1, i32 %arg2, i32 %arg3) {
-; GCN-LABEL: test43:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_max_u32_e32 v0, v0, v1
-; GCN-NEXT: v_cmp_gt_u32_e32 vcc_lo, v0, v2
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test43:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_max_u32_e32 v0, v0, v1
+; CHECK-NEXT: v_cmp_gt_u32_e32 vcc_lo, v0, v2
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp ult i32 %arg3, %arg1
%cmp2 = icmp ult i32 %arg3, %arg2
%or = or i1 %cmp1, %cmp2
@@ -657,13 +656,13 @@ define i1 @test43(i32 %arg1, i32 %arg2, i32 %arg3) {
}
define i1 @test44(i32 %arg1, i32 %arg2, i32 %arg3) {
-; GCN-LABEL: test44:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_max_u32_e32 v0, v0, v1
-; GCN-NEXT: v_cmp_lt_u32_e32 vcc_lo, v0, v2
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test44:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_max_u32_e32 v0, v0, v1
+; CHECK-NEXT: v_cmp_lt_u32_e32 vcc_lo, v0, v2
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp ugt i32 %arg3, %arg1
%cmp2 = icmp ugt i32 %arg3, %arg2
%or = and i1 %cmp1, %cmp2
@@ -671,13 +670,13 @@ define i1 @test44(i32 %arg1, i32 %arg2, i32 %arg3) {
}
define i1 @test45(i32 %arg1, i32 %arg2, i32 %arg3) {
-; GCN-LABEL: test45:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_min_u32_e32 v0, v0, v1
-; GCN-NEXT: v_cmp_lt_u32_e32 vcc_lo, v0, v2
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test45:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_min_u32_e32 v0, v0, v1
+; CHECK-NEXT: v_cmp_lt_u32_e32 vcc_lo, v0, v2
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp ugt i32 %arg3, %arg1
%cmp2 = icmp ugt i32 %arg3, %arg2
%or = or i1 %cmp1, %cmp2
@@ -685,13 +684,13 @@ define i1 @test45(i32 %arg1, i32 %arg2, i32 %arg3) {
}
define i1 @test46(i32 %arg1, i32 %arg2, i32 %arg3) {
-; GCN-LABEL: test46:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_max_i32_e32 v0, v0, v1
-; GCN-NEXT: v_cmp_gt_i32_e32 vcc_lo, v0, v2
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test46:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_max_i32_e32 v0, v0, v1
+; CHECK-NEXT: v_cmp_gt_i32_e32 vcc_lo, v0, v2
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp slt i32 %arg3, %arg1
%cmp2 = icmp sgt i32 %arg2, %arg3
%or = or i1 %cmp1, %cmp2
@@ -699,13 +698,13 @@ define i1 @test46(i32 %arg1, i32 %arg2, i32 %arg3) {
}
define i1 @test47(i32 %arg1, i32 %arg2, i32 %arg3) {
-; GCN-LABEL: test47:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_max_i32_e32 v0, v0, v1
-; GCN-NEXT: v_cmp_gt_i32_e32 vcc_lo, v0, v2
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test47:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_max_i32_e32 v0, v0, v1
+; CHECK-NEXT: v_cmp_gt_i32_e32 vcc_lo, v0, v2
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp sgt i32 %arg1, %arg3
%cmp2 = icmp slt i32 %arg3, %arg2
%or = or i1 %cmp1, %cmp2
@@ -713,13 +712,13 @@ define i1 @test47(i32 %arg1, i32 %arg2, i32 %arg3) {
}
define i1 @test48(i32 %arg1, i32 %arg2, i32 %arg3) {
-; GCN-LABEL: test48:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_min_i32_e32 v0, v0, v1
-; GCN-NEXT: v_cmp_lt_i32_e32 vcc_lo, v0, v2
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test48:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_min_i32_e32 v0, v0, v1
+; CHECK-NEXT: v_cmp_lt_i32_e32 vcc_lo, v0, v2
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp slt i32 %arg1, %arg3
%cmp2 = icmp sgt i32 %arg3, %arg2
%or = or i1 %cmp1, %cmp2
@@ -727,13 +726,13 @@ define i1 @test48(i32 %arg1, i32 %arg2, i32 %arg3) {
}
define i1 @test49(i32 %arg1, i32 %arg2, i32 %arg3) {
-; GCN-LABEL: test49:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_min_i32_e32 v0, v0, v1
-; GCN-NEXT: v_cmp_lt_i32_e32 vcc_lo, v0, v2
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test49:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_min_i32_e32 v0, v0, v1
+; CHECK-NEXT: v_cmp_lt_i32_e32 vcc_lo, v0, v2
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp sgt i32 %arg3, %arg1
%cmp2 = icmp slt i32 %arg2, %arg3
%or = or i1 %cmp1, %cmp2
@@ -741,13 +740,13 @@ define i1 @test49(i32 %arg1, i32 %arg2, i32 %arg3) {
}
define i1 @test50(i32 %arg1, i32 %arg2, i32 %arg3) {
-; GCN-LABEL: test50:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_min_i32_e32 v0, v0, v1
-; GCN-NEXT: v_cmp_gt_i32_e32 vcc_lo, v0, v2
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test50:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_min_i32_e32 v0, v0, v1
+; CHECK-NEXT: v_cmp_gt_i32_e32 vcc_lo, v0, v2
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp slt i32 %arg3, %arg1
%cmp2 = icmp sgt i32 %arg2, %arg3
%and = and i1 %cmp1, %cmp2
@@ -755,13 +754,13 @@ define i1 @test50(i32 %arg1, i32 %arg2, i32 %arg3) {
}
define i1 @test51(i32 %arg1, i32 %arg2, i32 %arg3) {
-; GCN-LABEL: test51:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_min_i32_e32 v0, v0, v1
-; GCN-NEXT: v_cmp_gt_i32_e32 vcc_lo, v0, v2
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test51:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_min_i32_e32 v0, v0, v1
+; CHECK-NEXT: v_cmp_gt_i32_e32 vcc_lo, v0, v2
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp sgt i32 %arg1, %arg3
%cmp2 = icmp slt i32 %arg3, %arg2
%and = and i1 %cmp1, %cmp2
@@ -769,13 +768,13 @@ define i1 @test51(i32 %arg1, i32 %arg2, i32 %arg3) {
}
define i1 @test52(i32 %arg1, i32 %arg2, i32 %arg3) {
-; GCN-LABEL: test52:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_max_i32_e32 v0, v0, v1
-; GCN-NEXT: v_cmp_lt_i32_e32 vcc_lo, v0, v2
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test52:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_max_i32_e32 v0, v0, v1
+; CHECK-NEXT: v_cmp_lt_i32_e32 vcc_lo, v0, v2
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp slt i32 %arg1, %arg3
%cmp2 = icmp sgt i32 %arg3, %arg2
%and = and i1 %cmp1, %cmp2
@@ -783,13 +782,13 @@ define i1 @test52(i32 %arg1, i32 %arg2, i32 %arg3) {
}
define i1 @test53(i32 %arg1, i32 %arg2, i32 %arg3) {
-; GCN-LABEL: test53:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_max_i32_e32 v0, v0, v1
-; GCN-NEXT: v_cmp_lt_i32_e32 vcc_lo, v0, v2
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test53:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_max_i32_e32 v0, v0, v1
+; CHECK-NEXT: v_cmp_lt_i32_e32 vcc_lo, v0, v2
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp sgt i32 %arg3, %arg1
%cmp2 = icmp slt i32 %arg2, %arg3
%and = and i1 %cmp1, %cmp2
@@ -797,13 +796,14 @@ define i1 @test53(i32 %arg1, i32 %arg2, i32 %arg3) {
}
define i1 @test54(float %arg1, float %arg2, float %arg3) #0 {
-; GCN-LABEL: test54:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_min_f32_e32 v0, v0, v1
-; GCN-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v2
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test54:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v2
+; CHECK-NEXT: v_cmp_lt_f32_e64 s0, v1, v2
+; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = fcmp olt float %arg1, %arg3
%cmp2 = fcmp olt float %arg2, %arg3
%or1 = or i1 %cmp1, %cmp2
@@ -811,13 +811,14 @@ define i1 @test54(float %arg1, float %arg2, float %arg3) #0 {
}
define i1 @test55(double %arg1, double %arg2, double %arg3) #0 {
-; GCN-LABEL: test55:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3]
-; GCN-NEXT: v_cmp_le_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test55:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_cmp_le_f64_e32 vcc_lo, v[0:1], v[4:5]
+; CHECK-NEXT: v_cmp_le_f64_e64 s0, v[2:3], v[4:5]
+; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = fcmp ole double %arg1, %arg3
%cmp2 = fcmp ole double %arg2, %arg3
%or1 = or i1 %cmp1, %cmp2
@@ -825,13 +826,14 @@ define i1 @test55(double %arg1, double %arg2, double %arg3) #0 {
}
define i1 @test56(double %arg1, double %arg2, double %arg3) #0 {
-; GCN-LABEL: test56:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3]
-; GCN-NEXT: v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test56:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]
+; CHECK-NEXT: v_cmp_gt_f64_e64 s0, v[2:3], v[4:5]
+; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = fcmp ogt double %arg1, %arg3
%cmp2 = fcmp ogt double %arg2, %arg3
%or1 = or i1 %cmp1, %cmp2
@@ -839,13 +841,14 @@ define i1 @test56(double %arg1, double %arg2, double %arg3) #0 {
}
define i1 @test57(float %arg1, float %arg2, float %arg3) #0 {
-; GCN-LABEL: test57:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_max_f32_e32 v0, v0, v1
-; GCN-NEXT: v_cmp_ge_f32_e32 vcc_lo, v0, v2
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test57:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_cmp_ge_f32_e32 vcc_lo, v0, v2
+; CHECK-NEXT: v_cmp_ge_f32_e64 s0, v1, v2
+; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = fcmp oge float %arg1, %arg3
%cmp2 = fcmp oge float %arg2, %arg3
%or1 = or i1 %cmp1, %cmp2
@@ -853,21 +856,14 @@ define i1 @test57(float %arg1, float %arg2, float %arg3) #0 {
}
define i1 @test58(double %arg1, double %arg2, double %arg3) #0 {
-; GFX11-LABEL: test58:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3]
-; GFX11-NEXT: v_cmp_nle_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11NONANS-LABEL: test58:
-; GFX11NONANS: ; %bb.0:
-; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3]
-; GFX11NONANS-NEXT: v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test58:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_cmp_nle_f64_e32 vcc_lo, v[0:1], v[4:5]
+; CHECK-NEXT: v_cmp_nle_f64_e64 s0, v[2:3], v[4:5]
+; CHECK-NEXT: s_and_b32 s0, vcc_lo, s0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = fcmp ugt double %arg1, %arg3
%cmp2 = fcmp ugt double %arg2, %arg3
%and1 = and i1 %cmp1, %cmp2
@@ -875,21 +871,14 @@ define i1 @test58(double %arg1, double %arg2, double %arg3) #0 {
}
define i1 @test59(float %arg1, float %arg2, float %arg3) #0 {
-; GFX11-LABEL: test59:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_min_f32_e32 v0, v0, v1
-; GFX11-NEXT: v_cmp_nlt_f32_e32 vcc_lo, v0, v2
-; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11NONANS-LABEL: test59:
-; GFX11NONANS: ; %bb.0:
-; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT: v_min_f32_e32 v0, v0, v1
-; GFX11NONANS-NEXT: v_cmp_ge_f32_e32 vcc_lo, v0, v2
-; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test59:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_cmp_nlt_f32_e32 vcc_lo, v0, v2
+; CHECK-NEXT: v_cmp_nlt_f32_e64 s0, v1, v2
+; CHECK-NEXT: s_and_b32 s0, vcc_lo, s0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = fcmp uge float %arg1, %arg3
%cmp2 = fcmp uge float %arg2, %arg3
%and1 = and i1 %cmp1, %cmp2
@@ -897,21 +886,14 @@ define i1 @test59(float %arg1, float %arg2, float %arg3) #0 {
}
define i1 @test60(float %arg1, float %arg2, float %arg3) #0 {
-; GFX11-LABEL: test60:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_max_f32_e32 v0, v0, v1
-; GFX11-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v0, v2
-; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11NONANS-LABEL: test60:
-; GFX11NONANS: ; %bb.0:
-; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT: v_max_f32_e32 v0, v0, v1
-; GFX11NONANS-NEXT: v_cmp_le_f32_e32 vcc_lo, v0, v2
-; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test60:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v0, v2
+; CHECK-NEXT: v_cmp_ngt_f32_e64 s0, v1, v2
+; CHECK-NEXT: s_and_b32 s0, vcc_lo, s0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = fcmp ule float %arg1, %arg3
%cmp2 = fcmp ule float %arg2, %arg3
%and1 = and i1 %cmp1, %cmp2
@@ -919,21 +901,14 @@ define i1 @test60(float %arg1, float %arg2, float %arg3) #0 {
}
define i1 @test61(double %arg1, double %arg2, double %arg3) #0 {
-; GFX11-LABEL: test61:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3]
-; GFX11-NEXT: v_cmp_nge_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11NONANS-LABEL: test61:
-; GFX11NONANS: ; %bb.0:
-; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3]
-; GFX11NONANS-NEXT: v_cmp_lt_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test61:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_cmp_nge_f64_e32 vcc_lo, v[0:1], v[4:5]
+; CHECK-NEXT: v_cmp_nge_f64_e64 s0, v[2:3], v[4:5]
+; CHECK-NEXT: s_and_b32 s0, vcc_lo, s0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = fcmp ult double %arg1, %arg3
%cmp2 = fcmp ult double %arg2, %arg3
%and1 = and i1 %cmp1, %cmp2
@@ -941,14 +916,15 @@ define i1 @test61(double %arg1, double %arg2, double %arg3) #0 {
}
define i1 @test62(float %arg1, float %arg2, float %arg3) {
-; GCN-LABEL: test62:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_dual_add_f32 v0, 1.0, v0 :: v_dual_add_f32 v1, 2.0, v1
-; GCN-NEXT: v_min_f32_e32 v0, v0, v1
-; GCN-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v2
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test62:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_dual_add_f32 v0, 1.0, v0 :: v_dual_add_f32 v1, 2.0, v1
+; CHECK-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v2
+; CHECK-NEXT: v_cmp_lt_f32_e64 s0, v1, v2
+; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%add1 = fadd nnan float %arg1, 1.0
%add2 = fadd nnan float %arg2, 2.0
%cmp1 = fcmp nnan olt float %add1, %arg3
@@ -958,15 +934,16 @@ define i1 @test62(float %arg1, float %arg2, float %arg3) {
}
define i1 @test63(double %arg1, double %arg2, double %arg3) #0 {
-; GCN-LABEL: test63:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
-; GCN-NEXT: v_add_f64 v[2:3], v[2:3], 2.0
-; GCN-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3]
-; GCN-NEXT: v_cmp_le_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test63:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; CHECK-NEXT: v_add_f64 v[2:3], v[2:3], 2.0
+; CHECK-NEXT: v_cmp_le_f64_e32 vcc_lo, v[0:1], v[4:5]
+; CHECK-NEXT: v_cmp_le_f64_e64 s0, v[2:3], v[4:5]
+; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%add1 = fadd nnan double %arg1, 1.0
%add2 = fadd nnan double %arg2, 2.0
%cmp1 = fcmp nnan ole double %add1, %arg3
@@ -976,15 +953,16 @@ define i1 @test63(double %arg1, double %arg2, double %arg3) #0 {
}
define i1 @test64(double %arg1, double %arg2, double %arg3) #0 {
-; GCN-LABEL: test64:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
-; GCN-NEXT: v_add_f64 v[2:3], v[2:3], 2.0
-; GCN-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3]
-; GCN-NEXT: v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test64:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; CHECK-NEXT: v_add_f64 v[2:3], v[2:3], 2.0
+; CHECK-NEXT: v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]
+; CHECK-NEXT: v_cmp_gt_f64_e64 s0, v[2:3], v[4:5]
+; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%add1 = fadd nnan double %arg1, 1.0
%add2 = fadd nnan double %arg2, 2.0
%cmp1 = fcmp nnan ogt double %add1, %arg3
@@ -994,14 +972,15 @@ define i1 @test64(double %arg1, double %arg2, double %arg3) #0 {
}
define i1 @test65(float %arg1, float %arg2, float %arg3) {
-; GCN-LABEL: test65:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_dual_add_f32 v0, 1.0, v0 :: v_dual_add_f32 v1, 2.0, v1
-; GCN-NEXT: v_max_f32_e32 v0, v0, v1
-; GCN-NEXT: v_cmp_ge_f32_e32 vcc_lo, v0, v2
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test65:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_dual_add_f32 v0, 1.0, v0 :: v_dual_add_f32 v1, 2.0, v1
+; CHECK-NEXT: v_cmp_ge_f32_e32 vcc_lo, v0, v2
+; CHECK-NEXT: v_cmp_ge_f32_e64 s0, v1, v2
+; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%add1 = fadd nnan float %arg1, 1.0
%add2 = fadd nnan float %arg2, 2.0
%cmp1 = fcmp nnan oge float %add1, %arg3
@@ -1011,15 +990,16 @@ define i1 @test65(float %arg1, float %arg2, float %arg3) {
}
define i1 @test66(double %arg1, double %arg2, double %arg3) {
-; GCN-LABEL: test66:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
-; GCN-NEXT: v_add_f64 v[2:3], v[2:3], 2.0
-; GCN-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3]
-; GCN-NEXT: v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test66:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; CHECK-NEXT: v_add_f64 v[2:3], v[2:3], 2.0
+; CHECK-NEXT: v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]
+; CHECK-NEXT: v_cmp_gt_f64_e64 s0, v[2:3], v[4:5]
+; CHECK-NEXT: s_and_b32 s0, vcc_lo, s0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%add1 = fadd nnan double %arg1, 1.0
%add2 = fadd nnan double %arg2, 2.0
%cmp1 = fcmp nnan ugt double %add1, %arg3
@@ -1029,14 +1009,15 @@ define i1 @test66(double %arg1, double %arg2, double %arg3) {
}
define i1 @test67(float %arg1, float %arg2, float %arg3) #0 {
-; GCN-LABEL: test67:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_dual_add_f32 v0, 1.0, v0 :: v_dual_add_f32 v1, 2.0, v1
-; GCN-NEXT: v_min_f32_e32 v0, v0, v1
-; GCN-NEXT: v_cmp_ge_f32_e32 vcc_lo, v0, v2
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test67:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_dual_add_f32 v0, 1.0, v0 :: v_dual_add_f32 v1, 2.0, v1
+; CHECK-NEXT: v_cmp_ge_f32_e32 vcc_lo, v0, v2
+; CHECK-NEXT: v_cmp_ge_f32_e64 s0, v1, v2
+; CHECK-NEXT: s_and_b32 s0, vcc_lo, s0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%add1 = fadd nnan float %arg1, 1.0
%add2 = fadd nnan float %arg2, 2.0
%cmp1 = fcmp nnan uge float %add1, %arg3
@@ -1046,14 +1027,15 @@ define i1 @test67(float %arg1, float %arg2, float %arg3) #0 {
}
define i1 @test68(float %arg1, float %arg2, float %arg3) #0 {
-; GCN-LABEL: test68:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_dual_add_f32 v0, 1.0, v0 :: v_dual_add_f32 v1, 2.0, v1
-; GCN-NEXT: v_max_f32_e32 v0, v0, v1
-; GCN-NEXT: v_cmp_le_f32_e32 vcc_lo, v0, v2
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test68:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_dual_add_f32 v0, 1.0, v0 :: v_dual_add_f32 v1, 2.0, v1
+; CHECK-NEXT: v_cmp_le_f32_e32 vcc_lo, v0, v2
+; CHECK-NEXT: v_cmp_le_f32_e64 s0, v1, v2
+; CHECK-NEXT: s_and_b32 s0, vcc_lo, s0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%add1 = fadd nnan float %arg1, 1.0
%add2 = fadd nnan float %arg2, 2.0
%cmp1 = fcmp nnan ule float %add1, %arg3
@@ -1063,15 +1045,16 @@ define i1 @test68(float %arg1, float %arg2, float %arg3) #0 {
}
define i1 @test69(double %arg1, double %arg2, double %arg3) {
-; GCN-LABEL: test69:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
-; GCN-NEXT: v_add_f64 v[2:3], v[2:3], 2.0
-; GCN-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3]
-; GCN-NEXT: v_cmp_lt_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test69:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; CHECK-NEXT: v_add_f64 v[2:3], v[2:3], 2.0
+; CHECK-NEXT: v_cmp_lt_f64_e32 vcc_lo, v[0:1], v[4:5]
+; CHECK-NEXT: v_cmp_lt_f64_e64 s0, v[2:3], v[4:5]
+; CHECK-NEXT: s_and_b32 s0, vcc_lo, s0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%add1 = fadd nnan double %arg1, 1.0
%add2 = fadd nnan double %arg2, 2.0
%cmp1 = fcmp nnan ult double %add1, %arg3
@@ -1081,22 +1064,15 @@ define i1 @test69(double %arg1, double %arg2, double %arg3) {
}
define i1 @test70(float %arg1, float %arg2, float %arg3) {
-; GFX11-LABEL: test70:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1
-; GFX11-NEXT: v_min_f32_e32 v0, v0, v1
-; GFX11-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v2
-; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11NONANS-LABEL: test70:
-; GFX11NONANS: ; %bb.0:
-; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT: v_min_f32_e32 v0, v0, v1
-; GFX11NONANS-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v2
-; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test70:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1
+; CHECK-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v2
+; CHECK-NEXT: v_cmp_lt_f32_e64 s0, v1, v2
+; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%var1 = call float @llvm.canonicalize.f32(float %arg1)
%var2 = call float @llvm.canonicalize.f32(float %arg2)
%cmp1 = fcmp olt float %var1, %arg3
@@ -1106,15 +1082,16 @@ define i1 @test70(float %arg1, float %arg2, float %arg3) {
}
define i1 @test71(double %arg1, double %arg2, double %arg3) {
-; GCN-LABEL: test71:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]
-; GCN-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
-; GCN-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3]
-; GCN-NEXT: v_cmp_le_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test71:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]
+; CHECK-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
+; CHECK-NEXT: v_cmp_le_f64_e32 vcc_lo, v[0:1], v[4:5]
+; CHECK-NEXT: v_cmp_le_f64_e64 s0, v[2:3], v[4:5]
+; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%var1 = call double @llvm.canonicalize.f64(double %arg1)
%var2 = call double @llvm.canonicalize.f64(double %arg2)
%cmp1 = fcmp ole double %var1, %arg3
@@ -1124,15 +1101,16 @@ define i1 @test71(double %arg1, double %arg2, double %arg3) {
}
define i1 @test72(double %arg1, double %arg2, double %arg3) {
-; GCN-LABEL: test72:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]
-; GCN-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
-; GCN-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3]
-; GCN-NEXT: v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test72:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]
+; CHECK-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
+; CHECK-NEXT: v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]
+; CHECK-NEXT: v_cmp_gt_f64_e64 s0, v[2:3], v[4:5]
+; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%var1 = call double @llvm.canonicalize.f64(double %arg1)
%var2 = call double @llvm.canonicalize.f64(double %arg2)
%cmp1 = fcmp ogt double %var1, %arg3
@@ -1142,22 +1120,15 @@ define i1 @test72(double %arg1, double %arg2, double %arg3) {
}
define i1 @test73(float %arg1, float %arg2, float %arg3) {
-; GFX11-LABEL: test73:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1
-; GFX11-NEXT: v_max_f32_e32 v0, v0, v1
-; GFX11-NEXT: v_cmp_ge_f32_e32 vcc_lo, v0, v2
-; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11NONANS-LABEL: test73:
-; GFX11NONANS: ; %bb.0:
-; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT: v_max_f32_e32 v0, v0, v1
-; GFX11NONANS-NEXT: v_cmp_ge_f32_e32 vcc_lo, v0, v2
-; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test73:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1
+; CHECK-NEXT: v_cmp_ge_f32_e32 vcc_lo, v0, v2
+; CHECK-NEXT: v_cmp_ge_f32_e64 s0, v1, v2
+; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%var1 = call float @llvm.canonicalize.f32(float %arg1)
%var2 = call float @llvm.canonicalize.f32(float %arg2)
%cmp1 = fcmp oge float %var1, %arg3
@@ -1167,25 +1138,16 @@ define i1 @test73(float %arg1, float %arg2, float %arg3) {
}
define i1 @test74(double %arg1, double %arg2, double %arg3) {
-; GFX11-LABEL: test74:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]
-; GFX11-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
-; GFX11-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3]
-; GFX11-NEXT: v_cmp_nle_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11NONANS-LABEL: test74:
-; GFX11NONANS: ; %bb.0:
-; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]
-; GFX11NONANS-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
-; GFX11NONANS-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3]
-; GFX11NONANS-NEXT: v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test74:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]
+; CHECK-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
+; CHECK-NEXT: v_cmp_nle_f64_e32 vcc_lo, v[0:1], v[4:5]
+; CHECK-NEXT: v_cmp_nle_f64_e64 s0, v[2:3], v[4:5]
+; CHECK-NEXT: s_and_b32 s0, vcc_lo, s0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%var1 = call double @llvm.canonicalize.f64(double %arg1)
%var2 = call double @llvm.canonicalize.f64(double %arg2)
%cmp1 = fcmp ugt double %var1, %arg3
@@ -1195,22 +1157,15 @@ define i1 @test74(double %arg1, double %arg2, double %arg3) {
}
define i1 @test75(float %arg1, float %arg2, float %arg3) {
-; GFX11-LABEL: test75:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1
-; GFX11-NEXT: v_min_f32_e32 v0, v0, v1
-; GFX11-NEXT: v_cmp_nlt_f32_e32 vcc_lo, v0, v2
-; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11NONANS-LABEL: test75:
-; GFX11NONANS: ; %bb.0:
-; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT: v_min_f32_e32 v0, v0, v1
-; GFX11NONANS-NEXT: v_cmp_ge_f32_e32 vcc_lo, v0, v2
-; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test75:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1
+; CHECK-NEXT: v_cmp_nlt_f32_e32 vcc_lo, v0, v2
+; CHECK-NEXT: v_cmp_nlt_f32_e64 s0, v1, v2
+; CHECK-NEXT: s_and_b32 s0, vcc_lo, s0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%var1 = call float @llvm.canonicalize.f32(float %arg1)
%var2 = call float @llvm.canonicalize.f32(float %arg2)
%cmp1 = fcmp uge float %var1, %arg3
@@ -1220,22 +1175,15 @@ define i1 @test75(float %arg1, float %arg2, float %arg3) {
}
define i1 @test76(float %arg1, float %arg2, float %arg3) {
-; GFX11-LABEL: test76:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1
-; GFX11-NEXT: v_max_f32_e32 v0, v0, v1
-; GFX11-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v0, v2
-; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11NONANS-LABEL: test76:
-; GFX11NONANS: ; %bb.0:
-; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT: v_max_f32_e32 v0, v0, v1
-; GFX11NONANS-NEXT: v_cmp_le_f32_e32 vcc_lo, v0, v2
-; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test76:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1
+; CHECK-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v0, v2
+; CHECK-NEXT: v_cmp_ngt_f32_e64 s0, v1, v2
+; CHECK-NEXT: s_and_b32 s0, vcc_lo, s0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%var1 = call float @llvm.canonicalize.f32(float %arg1)
%var2 = call float @llvm.canonicalize.f32(float %arg2)
%cmp1 = fcmp ule float %var1, %arg3
@@ -1245,25 +1193,16 @@ define i1 @test76(float %arg1, float %arg2, float %arg3) {
}
define i1 @test77(double %arg1, double %arg2, double %arg3) {
-; GFX11-LABEL: test77:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]
-; GFX11-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
-; GFX11-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3]
-; GFX11-NEXT: v_cmp_nge_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11NONANS-LABEL: test77:
-; GFX11NONANS: ; %bb.0:
-; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]
-; GFX11NONANS-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
-; GFX11NONANS-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3]
-; GFX11NONANS-NEXT: v_cmp_lt_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test77:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]
+; CHECK-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
+; CHECK-NEXT: v_cmp_nge_f64_e32 vcc_lo, v[0:1], v[4:5]
+; CHECK-NEXT: v_cmp_nge_f64_e64 s0, v[2:3], v[4:5]
+; CHECK-NEXT: s_and_b32 s0, vcc_lo, s0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%var1 = call double @llvm.canonicalize.f64(double %arg1)
%var2 = call double @llvm.canonicalize.f64(double %arg2)
%cmp1 = fcmp ult double %var1, %arg3
@@ -1273,13 +1212,14 @@ define i1 @test77(double %arg1, double %arg2, double %arg3) {
}
define i1 @test78(float %arg1, float %arg2, float %arg3) #0 {
-; GCN-LABEL: test78:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_min_f32_e32 v0, v0, v1
-; GCN-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v2
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test78:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v2
+; CHECK-NEXT: v_cmp_gt_f32_e64 s0, v2, v1
+; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = fcmp olt float %arg1, %arg3
%cmp2 = fcmp ogt float %arg3, %arg2
%or1 = or i1 %cmp1, %cmp2
@@ -1287,21 +1227,14 @@ define i1 @test78(float %arg1, float %arg2, float %arg3) #0 {
}
define i1 @test79(float %arg1, float %arg2, float %arg3) #0 {
-; GFX11-LABEL: test79:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_max_f32_e32 v0, v0, v1
-; GFX11-NEXT: v_cmp_nge_f32_e32 vcc_lo, v0, v2
-; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11NONANS-LABEL: test79:
-; GFX11NONANS: ; %bb.0:
-; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT: v_max_f32_e32 v0, v0, v1
-; GFX11NONANS-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v2
-; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test79:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_cmp_nge_f32_e32 vcc_lo, v0, v2
+; CHECK-NEXT: v_cmp_nle_f32_e64 s0, v2, v1
+; CHECK-NEXT: s_and_b32 s0, vcc_lo, s0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = fcmp ult float %arg1, %arg3
%cmp2 = fcmp ugt float %arg3, %arg2
%and1 = and i1 %cmp1, %cmp2
@@ -1309,14 +1242,15 @@ define i1 @test79(float %arg1, float %arg2, float %arg3) #0 {
}
define i1 @test80(float %arg1, float %arg2, float %arg3) {
-; GCN-LABEL: test80:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_dual_add_f32 v0, 1.0, v0 :: v_dual_add_f32 v1, 2.0, v1
-; GCN-NEXT: v_max_f32_e32 v0, v0, v1
-; GCN-NEXT: v_cmp_ge_f32_e32 vcc_lo, v0, v2
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test80:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_dual_add_f32 v0, 1.0, v0 :: v_dual_add_f32 v1, 2.0, v1
+; CHECK-NEXT: v_cmp_ge_f32_e32 vcc_lo, v0, v2
+; CHECK-NEXT: v_cmp_le_f32_e64 s0, v2, v1
+; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%add1 = fadd nnan float %arg1, 1.0
%add2 = fadd nnan float %arg2, 2.0
%cmp1 = fcmp nnan oge float %add1, %arg3
@@ -1326,15 +1260,16 @@ define i1 @test80(float %arg1, float %arg2, float %arg3) {
}
define i1 @test81(double %arg1, double %arg2, double %arg3) {
-; GCN-LABEL: test81:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
-; GCN-NEXT: v_add_f64 v[2:3], v[2:3], 2.0
-; GCN-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3]
-; GCN-NEXT: v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test81:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
+; CHECK-NEXT: v_add_f64 v[2:3], v[2:3], 2.0
+; CHECK-NEXT: v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]
+; CHECK-NEXT: v_cmp_lt_f64_e64 s0, v[4:5], v[2:3]
+; CHECK-NEXT: s_and_b32 s0, vcc_lo, s0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%add1 = fadd nnan double %arg1, 1.0
%add2 = fadd nnan double %arg2, 2.0
%cmp1 = fcmp nnan ugt double %add1, %arg3
@@ -1344,15 +1279,16 @@ define i1 @test81(double %arg1, double %arg2, double %arg3) {
}
define i1 @test82(double %arg1, double %arg2, double %arg3) {
-; GCN-LABEL: test82:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]
-; GCN-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
-; GCN-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3]
-; GCN-NEXT: v_cmp_le_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test82:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]
+; CHECK-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
+; CHECK-NEXT: v_cmp_le_f64_e32 vcc_lo, v[0:1], v[4:5]
+; CHECK-NEXT: v_cmp_ge_f64_e64 s0, v[4:5], v[2:3]
+; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%var1 = call double @llvm.canonicalize.f64(double %arg1)
%var2 = call double @llvm.canonicalize.f64(double %arg2)
%cmp1 = fcmp ole double %var1, %arg3
@@ -1362,22 +1298,15 @@ define i1 @test82(double %arg1, double %arg2, double %arg3) {
}
define i1 @test83(float %arg1, float %arg2, float %arg3) {
-; GFX11-LABEL: test83:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1
-; GFX11-NEXT: v_max_f32_e32 v0, v0, v1
-; GFX11-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v0, v2
-; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11NONANS-LABEL: test83:
-; GFX11NONANS: ; %bb.0:
-; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT: v_max_f32_e32 v0, v0, v1
-; GFX11NONANS-NEXT: v_cmp_le_f32_e32 vcc_lo, v0, v2
-; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test83:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1
+; CHECK-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v0, v2
+; CHECK-NEXT: v_cmp_nlt_f32_e64 s0, v2, v1
+; CHECK-NEXT: s_and_b32 s0, vcc_lo, s0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%var1 = call float @llvm.canonicalize.f32(float %arg1)
%var2 = call float @llvm.canonicalize.f32(float %arg2)
%cmp1 = fcmp ule float %var1, %arg3
@@ -1387,23 +1316,16 @@ define i1 @test83(float %arg1, float %arg2, float %arg3) {
}
define i1 @test84(half %arg1, half %arg2, half %arg3) {
-; GFX11-LABEL: test84:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_max_f16_e32 v0, v0, v0
-; GFX11-NEXT: v_max_f16_e32 v1, v1, v1
-; GFX11-NEXT: v_min_f16_e32 v0, v0, v1
-; GFX11-NEXT: v_cmp_lt_f16_e32 vcc_lo, v0, v2
-; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11NONANS-LABEL: test84:
-; GFX11NONANS: ; %bb.0:
-; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT: v_min_f16_e32 v0, v0, v1
-; GFX11NONANS-NEXT: v_cmp_lt_f16_e32 vcc_lo, v0, v2
-; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test84:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_max_f16_e32 v0, v0, v0
+; CHECK-NEXT: v_max_f16_e32 v1, v1, v1
+; CHECK-NEXT: v_cmp_lt_f16_e32 vcc_lo, v0, v2
+; CHECK-NEXT: v_cmp_lt_f16_e64 s0, v1, v2
+; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%var1 = call half @llvm.canonicalize.f16(half %arg1)
%var2 = call half @llvm.canonicalize.f16(half %arg2)
%cmp1 = fcmp olt half %var1, %arg3
@@ -1413,31 +1335,23 @@ define i1 @test84(half %arg1, half %arg2, half %arg3) {
}
define <2 x i1> @test85(<2 x half> %arg1, <2 x half> %arg2, <2 x half> %arg3) {
-; GFX11-LABEL: test85:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_pk_max_f16 v0, v0, v0
-; GFX11-NEXT: v_pk_max_f16 v1, v1, v1
-; GFX11-NEXT: v_pk_min_f16 v0, v0, v1
-; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; GFX11-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX11-NEXT: v_cmp_le_f16_e32 vcc_lo, v0, v2
-; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-NEXT: v_cmp_le_f16_e32 vcc_lo, v3, v1
-; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; GFX11-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11NONANS-LABEL: test85:
-; GFX11NONANS: ; %bb.0:
-; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT: v_pk_min_f16 v0, v0, v1
-; GFX11NONANS-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; GFX11NONANS-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX11NONANS-NEXT: v_cmp_le_f16_e32 vcc_lo, v0, v2
-; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT: v_cmp_le_f16_e32 vcc_lo, v3, v1
-; GFX11NONANS-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test85:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_pk_max_f16 v0, v0, v0
+; CHECK-NEXT: v_pk_max_f16 v1, v1, v1
+; CHECK-NEXT: v_lshrrev_b32_e32 v3, 16, v2
+; CHECK-NEXT: v_lshrrev_b32_e32 v4, 16, v0
+; CHECK-NEXT: v_lshrrev_b32_e32 v5, 16, v1
+; CHECK-NEXT: v_cmp_le_f16_e32 vcc_lo, v0, v2
+; CHECK-NEXT: v_cmp_le_f16_e64 s0, v1, v2
+; CHECK-NEXT: v_cmp_le_f16_e64 s1, v4, v3
+; CHECK-NEXT: v_cmp_le_f16_e64 s2, v5, v3
+; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_or_b32 s0, s1, s2
+; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%var1 = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> %arg1)
%var2 = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> %arg2)
%cmp1 = fcmp ole <2 x half> %var1, %arg3
@@ -1447,31 +1361,23 @@ define <2 x i1> @test85(<2 x half> %arg1, <2 x half> %arg2, <2 x half> %arg3) {
}
define <2 x i1> @test86(<2 x half> %arg1, <2 x half> %arg2, <2 x half> %arg3) {
-; GFX11-LABEL: test86:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_pk_max_f16 v0, v0, v0
-; GFX11-NEXT: v_pk_max_f16 v1, v1, v1
-; GFX11-NEXT: v_pk_max_f16 v0, v0, v1
-; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; GFX11-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX11-NEXT: v_cmp_gt_f16_e32 vcc_lo, v0, v2
-; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-NEXT: v_cmp_gt_f16_e32 vcc_lo, v3, v1
-; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; GFX11-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11NONANS-LABEL: test86:
-; GFX11NONANS: ; %bb.0:
-; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT: v_pk_max_f16 v0, v0, v1
-; GFX11NONANS-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; GFX11NONANS-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX11NONANS-NEXT: v_cmp_gt_f16_e32 vcc_lo, v0, v2
-; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT: v_cmp_gt_f16_e32 vcc_lo, v3, v1
-; GFX11NONANS-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test86:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_pk_max_f16 v0, v0, v0
+; CHECK-NEXT: v_pk_max_f16 v1, v1, v1
+; CHECK-NEXT: v_lshrrev_b32_e32 v3, 16, v2
+; CHECK-NEXT: v_lshrrev_b32_e32 v4, 16, v0
+; CHECK-NEXT: v_lshrrev_b32_e32 v5, 16, v1
+; CHECK-NEXT: v_cmp_gt_f16_e32 vcc_lo, v0, v2
+; CHECK-NEXT: v_cmp_gt_f16_e64 s0, v1, v2
+; CHECK-NEXT: v_cmp_gt_f16_e64 s1, v4, v3
+; CHECK-NEXT: v_cmp_gt_f16_e64 s2, v5, v3
+; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_or_b32 s0, s1, s2
+; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%var1 = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> %arg1)
%var2 = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> %arg2)
%cmp1 = fcmp ogt <2 x half> %var1, %arg3
@@ -1481,23 +1387,16 @@ define <2 x i1> @test86(<2 x half> %arg1, <2 x half> %arg2, <2 x half> %arg3) {
}
define i1 @test87(half %arg1, half %arg2, half %arg3) {
-; GFX11-LABEL: test87:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_max_f16_e32 v0, v0, v0
-; GFX11-NEXT: v_max_f16_e32 v1, v1, v1
-; GFX11-NEXT: v_max_f16_e32 v0, v0, v1
-; GFX11-NEXT: v_cmp_ge_f16_e32 vcc_lo, v0, v2
-; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11NONANS-LABEL: test87:
-; GFX11NONANS: ; %bb.0:
-; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT: v_max_f16_e32 v0, v0, v1
-; GFX11NONANS-NEXT: v_cmp_ge_f16_e32 vcc_lo, v0, v2
-; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test87:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_max_f16_e32 v0, v0, v0
+; CHECK-NEXT: v_max_f16_e32 v1, v1, v1
+; CHECK-NEXT: v_cmp_ge_f16_e32 vcc_lo, v0, v2
+; CHECK-NEXT: v_cmp_ge_f16_e64 s0, v1, v2
+; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%var1 = call half @llvm.canonicalize.f16(half %arg1)
%var2 = call half @llvm.canonicalize.f16(half %arg2)
%cmp1 = fcmp oge half %var1, %arg3
@@ -1507,31 +1406,23 @@ define i1 @test87(half %arg1, half %arg2, half %arg3) {
}
define <2 x i1> @test88(<2 x half> %arg1, <2 x half> %arg2, <2 x half> %arg3) {
-; GFX11-LABEL: test88:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_pk_max_f16 v0, v0, v0
-; GFX11-NEXT: v_pk_max_f16 v1, v1, v1
-; GFX11-NEXT: v_pk_min_f16 v0, v0, v1
-; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; GFX11-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX11-NEXT: v_cmp_nle_f16_e32 vcc_lo, v0, v2
-; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-NEXT: v_cmp_nle_f16_e32 vcc_lo, v3, v1
-; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; GFX11-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11NONANS-LABEL: test88:
-; GFX11NONANS: ; %bb.0:
-; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT: v_pk_min_f16 v0, v0, v1
-; GFX11NONANS-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; GFX11NONANS-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX11NONANS-NEXT: v_cmp_gt_f16_e32 vcc_lo, v0, v2
-; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT: v_cmp_gt_f16_e32 vcc_lo, v3, v1
-; GFX11NONANS-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test88:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_pk_max_f16 v0, v0, v0
+; CHECK-NEXT: v_pk_max_f16 v1, v1, v1
+; CHECK-NEXT: v_lshrrev_b32_e32 v3, 16, v2
+; CHECK-NEXT: v_lshrrev_b32_e32 v4, 16, v0
+; CHECK-NEXT: v_lshrrev_b32_e32 v5, 16, v1
+; CHECK-NEXT: v_cmp_nle_f16_e32 vcc_lo, v0, v2
+; CHECK-NEXT: v_cmp_nle_f16_e64 s0, v1, v2
+; CHECK-NEXT: v_cmp_nle_f16_e64 s1, v4, v3
+; CHECK-NEXT: v_cmp_nle_f16_e64 s2, v5, v3
+; CHECK-NEXT: s_and_b32 s0, vcc_lo, s0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_and_b32 s0, s1, s2
+; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%var1 = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> %arg1)
%var2 = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> %arg2)
%cmp1 = fcmp ugt <2 x half> %var1, %arg3
@@ -1541,23 +1432,16 @@ define <2 x i1> @test88(<2 x half> %arg1, <2 x half> %arg2, <2 x half> %arg3) {
}
define i1 @test89(half %arg1, half %arg2, half %arg3) {
-; GFX11-LABEL: test89:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_max_f16_e32 v0, v0, v0
-; GFX11-NEXT: v_max_f16_e32 v1, v1, v1
-; GFX11-NEXT: v_min_f16_e32 v0, v0, v1
-; GFX11-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v0, v2
-; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11NONANS-LABEL: test89:
-; GFX11NONANS: ; %bb.0:
-; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT: v_min_f16_e32 v0, v0, v1
-; GFX11NONANS-NEXT: v_cmp_ge_f16_e32 vcc_lo, v0, v2
-; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test89:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_max_f16_e32 v0, v0, v0
+; CHECK-NEXT: v_max_f16_e32 v1, v1, v1
+; CHECK-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v0, v2
+; CHECK-NEXT: v_cmp_nlt_f16_e64 s0, v1, v2
+; CHECK-NEXT: s_and_b32 s0, vcc_lo, s0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%var1 = call half @llvm.canonicalize.f16(half %arg1)
%var2 = call half @llvm.canonicalize.f16(half %arg2)
%cmp1 = fcmp uge half %var1, %arg3
@@ -1567,23 +1451,16 @@ define i1 @test89(half %arg1, half %arg2, half %arg3) {
}
define i1 @test90(half %arg1, half %arg2, half %arg3) {
-; GFX11-LABEL: test90:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_max_f16_e32 v0, v0, v0
-; GFX11-NEXT: v_max_f16_e32 v1, v1, v1
-; GFX11-NEXT: v_max_f16_e32 v0, v0, v1
-; GFX11-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0, v2
-; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11NONANS-LABEL: test90:
-; GFX11NONANS: ; %bb.0:
-; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT: v_max_f16_e32 v0, v0, v1
-; GFX11NONANS-NEXT: v_cmp_le_f16_e32 vcc_lo, v0, v2
-; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test90:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_max_f16_e32 v0, v0, v0
+; CHECK-NEXT: v_max_f16_e32 v1, v1, v1
+; CHECK-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0, v2
+; CHECK-NEXT: v_cmp_ngt_f16_e64 s0, v1, v2
+; CHECK-NEXT: s_and_b32 s0, vcc_lo, s0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%var1 = call half @llvm.canonicalize.f16(half %arg1)
%var2 = call half @llvm.canonicalize.f16(half %arg2)
%cmp1 = fcmp ule half %var1, %arg3
@@ -1593,31 +1470,23 @@ define i1 @test90(half %arg1, half %arg2, half %arg3) {
}
define <2 x i1> @test91(<2 x half> %arg1, <2 x half> %arg2, <2 x half> %arg3) {
-; GFX11-LABEL: test91:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_pk_max_f16 v0, v0, v0
-; GFX11-NEXT: v_pk_max_f16 v1, v1, v1
-; GFX11-NEXT: v_pk_max_f16 v0, v0, v1
-; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; GFX11-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX11-NEXT: v_cmp_nge_f16_e32 vcc_lo, v0, v2
-; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-NEXT: v_cmp_nge_f16_e32 vcc_lo, v3, v1
-; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; GFX11-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11NONANS-LABEL: test91:
-; GFX11NONANS: ; %bb.0:
-; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT: v_pk_max_f16 v0, v0, v1
-; GFX11NONANS-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; GFX11NONANS-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX11NONANS-NEXT: v_cmp_lt_f16_e32 vcc_lo, v0, v2
-; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT: v_cmp_lt_f16_e32 vcc_lo, v3, v1
-; GFX11NONANS-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test91:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_pk_max_f16 v0, v0, v0
+; CHECK-NEXT: v_pk_max_f16 v1, v1, v1
+; CHECK-NEXT: v_lshrrev_b32_e32 v3, 16, v2
+; CHECK-NEXT: v_lshrrev_b32_e32 v4, 16, v0
+; CHECK-NEXT: v_lshrrev_b32_e32 v5, 16, v1
+; CHECK-NEXT: v_cmp_nge_f16_e32 vcc_lo, v0, v2
+; CHECK-NEXT: v_cmp_nge_f16_e64 s0, v1, v2
+; CHECK-NEXT: v_cmp_nge_f16_e64 s1, v4, v3
+; CHECK-NEXT: v_cmp_nge_f16_e64 s2, v5, v3
+; CHECK-NEXT: s_and_b32 s0, vcc_lo, s0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_and_b32 s0, s1, s2
+; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%var1 = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> %arg1)
%var2 = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> %arg2)
%cmp1 = fcmp ult <2 x half> %var1, %arg3
@@ -1627,13 +1496,13 @@ define <2 x i1> @test91(<2 x half> %arg1, <2 x half> %arg2, <2 x half> %arg3) {
}
define i1 @test92(i32 %arg1, i32 %arg2, i32 %arg3, i32 %C) {
-; GCN-LABEL: test92:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_min3_u32 v0, v0, v1, v2
-; GCN-NEXT: v_cmp_lt_u32_e32 vcc_lo, v0, v3
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test92:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_min3_u32 v0, v0, v1, v2
+; CHECK-NEXT: v_cmp_lt_u32_e32 vcc_lo, v0, v3
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp ult i32 %arg1, %C
%cmp2 = icmp ult i32 %arg2, %C
%cmp3 = icmp ult i32 %arg3, %C
@@ -1643,16 +1512,16 @@ define i1 @test92(i32 %arg1, i32 %arg2, i32 %arg3, i32 %C) {
}
define i1 @test93(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %C) {
-; GCN-LABEL: test93:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_min_u32_e32 v0, v0, v1
-; GCN-NEXT: v_max_u32_e32 v1, v2, v3
-; GCN-NEXT: v_cmp_lt_u32_e32 vcc_lo, v0, v4
-; GCN-NEXT: v_cmp_gt_u32_e64 s0, v1, v4
-; GCN-NEXT: s_or_b32 s0, vcc_lo, s0
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test93:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_min_u32_e32 v0, v0, v1
+; CHECK-NEXT: v_max_u32_e32 v1, v2, v3
+; CHECK-NEXT: v_cmp_lt_u32_e32 vcc_lo, v0, v4
+; CHECK-NEXT: v_cmp_gt_u32_e64 s0, v1, v4
+; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp ult i32 %arg1, %C
%cmp2 = icmp ult i32 %arg2, %C
%cmp3 = icmp ugt i32 %arg3, %C
@@ -1664,16 +1533,16 @@ define i1 @test93(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %C) {
}
define i1 @test94(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %arg7, i32 %arg8, i32 %C) {
-; GCN-LABEL: test94:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_min_u32_e32 v2, v2, v3
-; GCN-NEXT: v_min3_u32 v0, v0, v1, v2
-; GCN-NEXT: v_min_u32_e32 v0, v0, v4
-; GCN-NEXT: v_min3_u32 v0, v5, v6, v0
-; GCN-NEXT: v_cmp_lt_u32_e32 vcc_lo, v0, v8
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test94:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_min_u32_e32 v2, v2, v3
+; CHECK-NEXT: v_min3_u32 v0, v0, v1, v2
+; CHECK-NEXT: v_min_u32_e32 v0, v0, v4
+; CHECK-NEXT: v_min3_u32 v0, v5, v6, v0
+; CHECK-NEXT: v_cmp_lt_u32_e32 vcc_lo, v0, v8
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp ult i32 %arg1, %C
%cmp2 = icmp ult i32 %arg2, %C
%or1 = or i1 %cmp1, %cmp2
@@ -1693,13 +1562,13 @@ define i1 @test94(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %ar
}
define i1 @test95(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %C) {
-; GCN-LABEL: test95:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_maxmin_u32 v0, v0, v1, v2
-; GCN-NEXT: v_cmp_lt_u32_e32 vcc_lo, v0, v4
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test95:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_maxmin_u32 v0, v0, v1, v2
+; CHECK-NEXT: v_cmp_lt_u32_e32 vcc_lo, v0, v4
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp ult i32 %arg1, %C
%cmp2 = icmp ult i32 %arg2, %C
%cmp3 = icmp ult i32 %arg3, %C
@@ -1709,13 +1578,13 @@ define i1 @test95(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %C) {
}
define i1 @test96(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %C) {
-; GCN-LABEL: test96:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_minmax_u32 v0, v0, v1, v2
-; GCN-NEXT: v_cmp_lt_u32_e32 vcc_lo, v0, v4
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test96:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_minmax_u32 v0, v0, v1, v2
+; CHECK-NEXT: v_cmp_lt_u32_e32 vcc_lo, v0, v4
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp ult i32 %arg1, %C
%cmp2 = icmp ult i32 %arg2, %C
%cmp3 = icmp ult i32 %arg3, %C
@@ -1725,14 +1594,14 @@ define i1 @test96(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %C) {
}
define i1 @test97(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %C) {
-; GCN-LABEL: test97:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_min_u32_e32 v0, v0, v1
-; GCN-NEXT: v_max3_u32 v0, v0, v2, v3
-; GCN-NEXT: v_cmp_lt_u32_e32 vcc_lo, v0, v4
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test97:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_min_u32_e32 v0, v0, v1
+; CHECK-NEXT: v_max3_u32 v0, v0, v2, v3
+; CHECK-NEXT: v_cmp_lt_u32_e32 vcc_lo, v0, v4
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp ult i32 %arg1, %C
%cmp2 = icmp ult i32 %arg2, %C
%cmp3 = icmp ult i32 %arg3, %C
@@ -1744,14 +1613,14 @@ define i1 @test97(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %C) {
}
define i1 @test98(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %C) {
-; GCN-LABEL: test98:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_min_u32_e32 v2, v2, v3
-; GCN-NEXT: v_minmax_u32 v0, v0, v1, v2
-; GCN-NEXT: v_cmp_lt_u32_e32 vcc_lo, v0, v4
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test98:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_min_u32_e32 v2, v2, v3
+; CHECK-NEXT: v_minmax_u32 v0, v0, v1, v2
+; CHECK-NEXT: v_cmp_lt_u32_e32 vcc_lo, v0, v4
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp ult i32 %arg1, %C
%cmp2 = icmp ult i32 %arg2, %C
%cmp3 = icmp ult i32 %arg3, %C
@@ -1763,14 +1632,14 @@ define i1 @test98(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %C) {
}
define i1 @test99(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %C) {
-; GCN-LABEL: test99:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_max_u32_e32 v2, v2, v3
-; GCN-NEXT: v_min3_u32 v0, v0, v1, v2
-; GCN-NEXT: v_cmp_lt_u32_e32 vcc_lo, v0, v4
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test99:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_max_u32_e32 v2, v2, v3
+; CHECK-NEXT: v_min3_u32 v0, v0, v1, v2
+; CHECK-NEXT: v_cmp_lt_u32_e32 vcc_lo, v0, v4
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp ult i32 %arg1, %C
%cmp2 = icmp ult i32 %arg2, %C
%cmp3 = icmp ult i32 %arg3, %C
@@ -1782,14 +1651,14 @@ define i1 @test99(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %C) {
}
define i1 @test100(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %C) {
-; GCN-LABEL: test100:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_max_u32_e32 v2, v2, v3
-; GCN-NEXT: v_maxmin_u32 v0, v0, v1, v2
-; GCN-NEXT: v_cmp_lt_u32_e32 vcc_lo, v0, v4
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test100:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_max_u32_e32 v2, v2, v3
+; CHECK-NEXT: v_maxmin_u32 v0, v0, v1, v2
+; CHECK-NEXT: v_cmp_lt_u32_e32 vcc_lo, v0, v4
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp ult i32 %arg1, %C
%cmp2 = icmp ult i32 %arg2, %C
%cmp3 = icmp ult i32 %arg3, %C
@@ -1801,15 +1670,15 @@ define i1 @test100(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %C) {
}
define i1 @test101(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %C) {
-; GCN-LABEL: test101:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_max_u32_e32 v0, v0, v1
-; GCN-NEXT: v_minmax_u32 v1, v3, v4, v5
-; GCN-NEXT: v_min3_u32 v0, v0, v2, v1
-; GCN-NEXT: v_cmp_lt_u32_e32 vcc_lo, v0, v6
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test101:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_max_u32_e32 v0, v0, v1
+; CHECK-NEXT: v_minmax_u32 v1, v3, v4, v5
+; CHECK-NEXT: v_min3_u32 v0, v0, v2, v1
+; CHECK-NEXT: v_cmp_lt_u32_e32 vcc_lo, v0, v6
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp ult i32 %arg1, %C
%cmp2 = icmp ult i32 %arg2, %C
%cmp3 = icmp ult i32 %arg3, %C
@@ -1825,15 +1694,15 @@ define i1 @test101(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %a
}
define i1 @test102(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %C) {
-; GCN-LABEL: test102:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_max_u32_e32 v0, v0, v1
-; GCN-NEXT: v_min_u32_e32 v1, v2, v3
-; GCN-NEXT: v_min3_u32 v0, v0, v5, v1
-; GCN-NEXT: v_cmp_lt_u32_e32 vcc_lo, v0, v6
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test102:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_max_u32_e32 v0, v0, v1
+; CHECK-NEXT: v_min_u32_e32 v1, v2, v3
+; CHECK-NEXT: v_min3_u32 v0, v0, v5, v1
+; CHECK-NEXT: v_cmp_lt_u32_e32 vcc_lo, v0, v6
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp ult i32 %arg1, %C
%cmp2 = icmp ult i32 %arg2, %C
%cmp3 = icmp ult i32 %arg3, %C
@@ -1850,17 +1719,17 @@ define i1 @test102(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %a
}
define i1 @test103(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %C) {
-; GCN-LABEL: test103:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_max_u32_e32 v4, v4, v5
-; GCN-NEXT: v_max_u32_e32 v2, v2, v3
-; GCN-NEXT: v_maxmin_u32 v0, v0, v1, v4
-; GCN-NEXT: v_cmp_gt_u32_e32 vcc_lo, v2, v6
-; GCN-NEXT: v_cmp_lt_u32_e64 s0, v0, v6
-; GCN-NEXT: s_or_b32 s0, s0, vcc_lo
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test103:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_max_u32_e32 v4, v4, v5
+; CHECK-NEXT: v_max_u32_e32 v2, v2, v3
+; CHECK-NEXT: v_maxmin_u32 v0, v0, v1, v4
+; CHECK-NEXT: v_cmp_gt_u32_e32 vcc_lo, v2, v6
+; CHECK-NEXT: v_cmp_lt_u32_e64 s0, v0, v6
+; CHECK-NEXT: s_or_b32 s0, s0, vcc_lo
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp ult i32 %arg1, %C
%cmp2 = icmp ult i32 %arg2, %C
%cmp3 = icmp ugt i32 %arg3, %C
@@ -1877,23 +1746,23 @@ define i1 @test103(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %a
define i1 @test104(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %arg7, i32 %arg8, i32 %arg9, i32 %arg10, i32 %C) {
-; GCN-LABEL: test104:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_min_u32_e32 v8, v8, v9
-; GCN-NEXT: v_max_u32_e32 v2, v2, v3
-; GCN-NEXT: v_min_u32_e32 v3, v4, v5
-; GCN-NEXT: v_max_u32_e32 v4, v6, v7
-; GCN-NEXT: v_min3_u32 v0, v0, v1, v8
-; GCN-NEXT: v_cmp_gt_u32_e32 vcc_lo, v2, v10
-; GCN-NEXT: v_cmp_lt_u32_e64 s0, v3, v10
-; GCN-NEXT: v_cmp_gt_u32_e64 s1, v4, v10
-; GCN-NEXT: v_cmp_lt_u32_e64 s2, v0, v10
-; GCN-NEXT: s_or_b32 s0, s0, s1
-; GCN-NEXT: s_or_b32 s1, s2, vcc_lo
-; GCN-NEXT: s_or_b32 s0, s0, s1
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test104:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_min_u32_e32 v8, v8, v9
+; CHECK-NEXT: v_max_u32_e32 v2, v2, v3
+; CHECK-NEXT: v_min_u32_e32 v3, v4, v5
+; CHECK-NEXT: v_max_u32_e32 v4, v6, v7
+; CHECK-NEXT: v_min3_u32 v0, v0, v1, v8
+; CHECK-NEXT: v_cmp_gt_u32_e32 vcc_lo, v2, v10
+; CHECK-NEXT: v_cmp_lt_u32_e64 s0, v3, v10
+; CHECK-NEXT: v_cmp_gt_u32_e64 s1, v4, v10
+; CHECK-NEXT: v_cmp_lt_u32_e64 s2, v0, v10
+; CHECK-NEXT: s_or_b32 s0, s0, s1
+; CHECK-NEXT: s_or_b32 s1, s2, vcc_lo
+; CHECK-NEXT: s_or_b32 s0, s0, s1
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp ult i32 %arg1, %C
%cmp2 = icmp ult i32 %arg2, %C
%cmp3 = icmp ugt i32 %arg3, %C
@@ -1917,22 +1786,22 @@ define i1 @test104(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %a
}
define i1 @test105(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %arg7, i32 %arg8, i32 %arg9, i32 %arg10, i32 %C) {
-; GCN-LABEL: test105:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_max_u32_e32 v0, v0, v1
-; GCN-NEXT: v_max_u32_e32 v1, v2, v3
-; GCN-NEXT: v_max_u32_e32 v2, v4, v5
-; GCN-NEXT: v_max_u32_e32 v3, v6, v7
-; GCN-NEXT: v_cmp_lt_u32_e32 vcc_lo, v0, v10
-; GCN-NEXT: v_cmp_gt_u32_e64 s0, v1, v10
-; GCN-NEXT: v_cmp_lt_u32_e64 s1, v2, v10
-; GCN-NEXT: v_cmp_gt_u32_e64 s2, v3, v10
-; GCN-NEXT: s_and_b32 s0, vcc_lo, s0
-; GCN-NEXT: s_or_b32 s1, s2, s1
-; GCN-NEXT: s_and_b32 s0, s0, s1
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test105:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_max_u32_e32 v0, v0, v1
+; CHECK-NEXT: v_max_u32_e32 v1, v2, v3
+; CHECK-NEXT: v_max_u32_e32 v2, v4, v5
+; CHECK-NEXT: v_max_u32_e32 v3, v6, v7
+; CHECK-NEXT: v_cmp_lt_u32_e32 vcc_lo, v0, v10
+; CHECK-NEXT: v_cmp_gt_u32_e64 s0, v1, v10
+; CHECK-NEXT: v_cmp_lt_u32_e64 s1, v2, v10
+; CHECK-NEXT: v_cmp_gt_u32_e64 s2, v3, v10
+; CHECK-NEXT: s_and_b32 s0, vcc_lo, s0
+; CHECK-NEXT: s_or_b32 s1, s2, s1
+; CHECK-NEXT: s_and_b32 s0, s0, s1
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp ult i32 %arg1, %C
%cmp2 = icmp ult i32 %arg2, %C
%cmp3 = icmp ugt i32 %arg3, %C
@@ -1952,24 +1821,24 @@ define i1 @test105(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %a
}
define i1 @test106(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %arg7, i32 %arg8, i32 %arg9, i32 %arg10, i32 %arg11, i32 %arg12, i32 %C1, i32 %C2) {
-; GCN-LABEL: test106:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_min_u32_e32 v6, v6, v7
-; GCN-NEXT: v_min_u32_e32 v0, v0, v1
-; GCN-NEXT: v_min_u32_e32 v1, v10, v11
-; GCN-NEXT: v_min_u32_e32 v2, v2, v3
-; GCN-NEXT: v_min3_u32 v3, v4, v5, v6
-; GCN-NEXT: v_cmp_lt_u32_e32 vcc_lo, v0, v12
-; GCN-NEXT: v_min3_u32 v0, v8, v9, v1
-; GCN-NEXT: v_cmp_lt_u32_e64 s0, v2, v13
-; GCN-NEXT: v_cmp_lt_u32_e64 s1, v3, v13
-; GCN-NEXT: v_cmp_lt_u32_e64 s2, v0, v12
-; GCN-NEXT: s_or_b32 s0, vcc_lo, s0
-; GCN-NEXT: s_or_b32 s0, s0, s1
-; GCN-NEXT: s_or_b32 s0, s2, s0
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test106:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_min_u32_e32 v6, v6, v7
+; CHECK-NEXT: v_min_u32_e32 v0, v0, v1
+; CHECK-NEXT: v_min_u32_e32 v1, v10, v11
+; CHECK-NEXT: v_min_u32_e32 v2, v2, v3
+; CHECK-NEXT: v_min3_u32 v3, v4, v5, v6
+; CHECK-NEXT: v_cmp_lt_u32_e32 vcc_lo, v0, v12
+; CHECK-NEXT: v_min3_u32 v0, v8, v9, v1
+; CHECK-NEXT: v_cmp_lt_u32_e64 s0, v2, v13
+; CHECK-NEXT: v_cmp_lt_u32_e64 s1, v3, v13
+; CHECK-NEXT: v_cmp_lt_u32_e64 s2, v0, v12
+; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0
+; CHECK-NEXT: s_or_b32 s0, s0, s1
+; CHECK-NEXT: s_or_b32 s0, s2, s0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp ult i32 %arg1, %C1
%cmp2 = icmp ult i32 %arg2, %C1
%cmp3 = icmp ult i32 %arg3, %C2
@@ -1997,13 +1866,16 @@ define i1 @test106(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %a
}
define i1 @test107(float %arg1, float %arg2, float %arg3, float %C) {
-; GCN-LABEL: test107:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_min3_f32 v0, v0, v1, v2
-; GCN-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v3
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test107:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v3
+; CHECK-NEXT: v_cmp_lt_f32_e64 s0, v1, v3
+; CHECK-NEXT: v_cmp_lt_f32_e64 s1, v2, v3
+; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0
+; CHECK-NEXT: s_or_b32 s0, s0, s1
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = fcmp olt float %arg1, %C
%cmp2 = fcmp olt float %arg2, %C
%cmp3 = fcmp olt float %arg3, %C
@@ -2013,21 +1885,16 @@ define i1 @test107(float %arg1, float %arg2, float %arg3, float %C) {
}
define i1 @test108(float %arg1, float %arg2, float %arg3, float %C) {
-; GFX11-LABEL: test108:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_max3_f32 v0, v0, v1, v2
-; GFX11-NEXT: v_cmp_nge_f32_e32 vcc_lo, v0, v3
-; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11NONANS-LABEL: test108:
-; GFX11NONANS: ; %bb.0:
-; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT: v_max3_f32 v0, v0, v1, v2
-; GFX11NONANS-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v3
-; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test108:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_cmp_nge_f32_e32 vcc_lo, v0, v3
+; CHECK-NEXT: v_cmp_nge_f32_e64 s0, v1, v3
+; CHECK-NEXT: v_cmp_nge_f32_e64 s1, v2, v3
+; CHECK-NEXT: s_and_b32 s0, vcc_lo, s0
+; CHECK-NEXT: s_and_b32 s0, s0, s1
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = fcmp ult float %arg1, %C
%cmp2 = fcmp ult float %arg2, %C
%cmp3 = fcmp ult float %arg3, %C
@@ -2037,27 +1904,18 @@ define i1 @test108(float %arg1, float %arg2, float %arg3, float %C) {
}
define i1 @test109(float %arg1, float %arg2, float %arg3, float %arg4, float %C) {
-; GFX11-LABEL: test109:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_dual_max_f32 v1, v1, v1 :: v_dual_max_f32 v0, v0, v0
-; GFX11-NEXT: v_dual_max_f32 v3, v3, v3 :: v_dual_max_f32 v2, v2, v2
-; GFX11-NEXT: v_dual_min_f32 v0, v0, v1 :: v_dual_max_f32 v1, v2, v3
-; GFX11-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v4
-; GFX11-NEXT: v_cmp_gt_f32_e64 s0, v1, v4
-; GFX11-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11NONANS-LABEL: test109:
-; GFX11NONANS: ; %bb.0:
-; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT: v_dual_min_f32 v0, v0, v1 :: v_dual_max_f32 v1, v2, v3
-; GFX11NONANS-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v4
-; GFX11NONANS-NEXT: v_cmp_gt_f32_e64 s0, v1, v4
-; GFX11NONANS-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
-; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test109:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v4
+; CHECK-NEXT: v_cmp_lt_f32_e64 s0, v1, v4
+; CHECK-NEXT: v_cmp_gt_f32_e64 s1, v2, v4
+; CHECK-NEXT: v_cmp_gt_f32_e64 s2, v3, v4
+; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0
+; CHECK-NEXT: s_or_b32 s1, s1, s2
+; CHECK-NEXT: s_or_b32 s0, s0, s1
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = fcmp olt float %arg1, %C
%cmp2 = fcmp olt float %arg2, %C
%cmp3 = fcmp ogt float %arg3, %C
@@ -2069,17 +1927,20 @@ define i1 @test109(float %arg1, float %arg2, float %arg3, float %arg4, float %C)
}
define i1 @test110(float %arg1, float %arg2, float %arg3, float %arg4, float %C1, float %C2, float %C3, float %C4, float %C) #0 {
-; GCN-LABEL: test110:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_dual_add_f32 v0, v0, v4 :: v_dual_add_f32 v1, v1, v5
-; GCN-NEXT: v_dual_add_f32 v2, v2, v6 :: v_dual_add_f32 v3, v3, v7
-; GCN-NEXT: v_dual_max_f32 v0, v0, v1 :: v_dual_min_f32 v1, v2, v3
-; GCN-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v8
-; GCN-NEXT: v_cmp_gt_f32_e64 s0, v1, v8
-; GCN-NEXT: s_and_b32 s0, vcc_lo, s0
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test110:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_dual_add_f32 v0, v0, v4 :: v_dual_add_f32 v1, v1, v5
+; CHECK-NEXT: v_dual_add_f32 v2, v2, v6 :: v_dual_add_f32 v3, v3, v7
+; CHECK-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v8
+; CHECK-NEXT: v_cmp_lt_f32_e64 s0, v1, v8
+; CHECK-NEXT: v_cmp_gt_f32_e64 s1, v2, v8
+; CHECK-NEXT: v_cmp_gt_f32_e64 s2, v3, v8
+; CHECK-NEXT: s_and_b32 s0, vcc_lo, s0
+; CHECK-NEXT: s_and_b32 s1, s1, s2
+; CHECK-NEXT: s_and_b32 s0, s0, s1
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%add1 = fadd nnan float %arg1, %C1
%add2 = fadd nnan float %arg2, %C2
%add3 = fadd nnan float %arg3, %C3
@@ -2095,28 +1956,24 @@ define i1 @test110(float %arg1, float %arg2, float %arg3, float %arg4, float %C1
}
define i1 @test111(float %arg1, float %arg2, float %arg3, float %arg4, float %arg5, float %arg6, float %arg7, float %arg8, float %C) {
-; GFX11-LABEL: test111:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_dual_max_f32 v3, v3, v3 :: v_dual_max_f32 v2, v2, v2
-; GFX11-NEXT: v_dual_min_f32 v2, v2, v3 :: v_dual_max_f32 v3, v4, v4
-; GFX11-NEXT: v_min3_f32 v0, v0, v1, v2
-; GFX11-NEXT: v_min_f32_e32 v0, v0, v3
-; GFX11-NEXT: v_min3_f32 v0, v5, v6, v0
-; GFX11-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v8
-; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11NONANS-LABEL: test111:
-; GFX11NONANS: ; %bb.0:
-; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT: v_min_f32_e32 v2, v2, v3
-; GFX11NONANS-NEXT: v_min3_f32 v0, v0, v1, v2
-; GFX11NONANS-NEXT: v_min_f32_e32 v0, v0, v4
-; GFX11NONANS-NEXT: v_min3_f32 v0, v5, v6, v0
-; GFX11NONANS-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v8
-; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test111:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v8
+; CHECK-NEXT: v_cmp_lt_f32_e64 s0, v1, v8
+; CHECK-NEXT: v_cmp_lt_f32_e64 s1, v2, v8
+; CHECK-NEXT: v_cmp_lt_f32_e64 s2, v3, v8
+; CHECK-NEXT: s_or_b32 s3, vcc_lo, s0
+; CHECK-NEXT: v_cmp_lt_f32_e32 vcc_lo, v4, v8
+; CHECK-NEXT: s_or_b32 s2, s1, s2
+; CHECK-NEXT: v_cmp_lt_f32_e64 s0, v5, v8
+; CHECK-NEXT: v_cmp_lt_f32_e64 s1, v6, v8
+; CHECK-NEXT: s_or_b32 s2, s3, s2
+; CHECK-NEXT: s_or_b32 s2, s2, vcc_lo
+; CHECK-NEXT: s_or_b32 s0, s0, s1
+; CHECK-NEXT: s_or_b32 s0, s0, s2
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = fcmp olt float %arg1, %C
%cmp2 = fcmp olt float %arg2, %C
%or1 = or i1 %cmp1, %cmp2
@@ -2136,30 +1993,24 @@ define i1 @test111(float %arg1, float %arg2, float %arg3, float %arg4, float %ar
}
define i1 @test112(float %arg1, float %arg2, float %arg3, float %arg4, float %arg5, float %arg6, float %arg7, float %arg8, float %C) {
-; GFX11-LABEL: test112:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_dual_max_f32 v3, v3, v3 :: v_dual_max_f32 v2, v2, v2
-; GFX11-NEXT: v_cmp_nge_f32_e32 vcc_lo, v4, v8
-; GFX11-NEXT: v_dual_max_f32 v5, v5, v5 :: v_dual_min_f32 v2, v2, v3
-; GFX11-NEXT: v_max_f32_e32 v3, v6, v6
-; GFX11-NEXT: v_min3_f32 v0, v0, v1, v2
-; GFX11-NEXT: v_min3_f32 v0, v0, v5, v3
-; GFX11-NEXT: v_cmp_lt_f32_e64 s0, v0, v8
-; GFX11-NEXT: s_or_b32 s0, s0, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11NONANS-LABEL: test112:
-; GFX11NONANS: ; %bb.0:
-; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT: v_min_f32_e32 v2, v2, v3
-; GFX11NONANS-NEXT: v_min3_f32 v0, v0, v1, v2
-; GFX11NONANS-NEXT: v_min_f32_e32 v0, v0, v4
-; GFX11NONANS-NEXT: v_min3_f32 v0, v5, v6, v0
-; GFX11NONANS-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v8
-; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test112:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v8
+; CHECK-NEXT: v_cmp_lt_f32_e64 s0, v1, v8
+; CHECK-NEXT: v_cmp_lt_f32_e64 s1, v2, v8
+; CHECK-NEXT: v_cmp_lt_f32_e64 s2, v3, v8
+; CHECK-NEXT: s_or_b32 s3, vcc_lo, s0
+; CHECK-NEXT: v_cmp_nge_f32_e32 vcc_lo, v4, v8
+; CHECK-NEXT: s_or_b32 s2, s1, s2
+; CHECK-NEXT: v_cmp_lt_f32_e64 s0, v5, v8
+; CHECK-NEXT: v_cmp_lt_f32_e64 s1, v6, v8
+; CHECK-NEXT: s_or_b32 s2, s3, s2
+; CHECK-NEXT: s_or_b32 s2, s2, vcc_lo
+; CHECK-NEXT: s_or_b32 s0, s0, s1
+; CHECK-NEXT: s_or_b32 s0, s0, s2
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = fcmp olt float %arg1, %C
%cmp2 = fcmp olt float %arg2, %C
%or1 = or i1 %cmp1, %cmp2
@@ -2179,24 +2030,16 @@ define i1 @test112(float %arg1, float %arg2, float %arg3, float %arg4, float %ar
}
define i1 @test113(float %arg1, float %arg2, float %arg3, float %C) {
-; GFX11-LABEL: test113:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_dual_max_f32 v1, v1, v1 :: v_dual_max_f32 v0, v0, v0
-; GFX11-NEXT: v_cmp_lt_f32_e32 vcc_lo, v2, v3
-; GFX11-NEXT: v_max_f32_e32 v0, v0, v1
-; GFX11-NEXT: v_cmp_nge_f32_e64 s0, v0, v3
-; GFX11-NEXT: s_or_b32 s0, s0, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11NONANS-LABEL: test113:
-; GFX11NONANS: ; %bb.0:
-; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT: v_maxmin_f32 v0, v0, v1, v2
-; GFX11NONANS-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v3
-; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test113:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_cmp_nge_f32_e32 vcc_lo, v0, v3
+; CHECK-NEXT: v_cmp_nge_f32_e64 s0, v1, v3
+; CHECK-NEXT: v_cmp_lt_f32_e64 s1, v2, v3
+; CHECK-NEXT: s_and_b32 s0, vcc_lo, s0
+; CHECK-NEXT: s_or_b32 s0, s0, s1
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = fcmp ult float %arg1, %C
%cmp2 = fcmp ult float %arg2, %C
%cmp3 = fcmp olt float %arg3, %C
@@ -2206,26 +2049,16 @@ define i1 @test113(float %arg1, float %arg2, float %arg3, float %C) {
}
define i1 @test114(float %arg1, float %arg2, float %arg3, float %C) {
-; GFX11-LABEL: test114:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_dual_max_f32 v1, v1, v1 :: v_dual_max_f32 v0, v0, v0
-; GFX11-NEXT: v_cmp_nge_f32_e32 vcc_lo, v2, v3
-; GFX11-NEXT: v_max_f32_e32 v0, v0, v1
-; GFX11-NEXT: v_cmp_gt_f32_e64 s0, v0, v3
-; GFX11-NEXT: s_and_b32 s0, s0, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11NONANS-LABEL: test114:
-; GFX11NONANS: ; %bb.0:
-; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT: v_max_f32_e32 v0, v0, v1
-; GFX11NONANS-NEXT: v_cmp_lt_f32_e32 vcc_lo, v2, v3
-; GFX11NONANS-NEXT: v_cmp_gt_f32_e64 s0, v0, v3
-; GFX11NONANS-NEXT: s_and_b32 s0, s0, vcc_lo
-; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
-; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test114:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_cmp_gt_f32_e32 vcc_lo, v0, v3
+; CHECK-NEXT: v_cmp_gt_f32_e64 s0, v1, v3
+; CHECK-NEXT: v_cmp_nge_f32_e64 s1, v2, v3
+; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0
+; CHECK-NEXT: s_and_b32 s0, s0, s1
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = fcmp ogt float %arg1, %C
%cmp2 = fcmp ogt float %arg2, %C
%cmp3 = fcmp ult float %arg3, %C
@@ -2235,26 +2068,19 @@ define i1 @test114(float %arg1, float %arg2, float %arg3, float %C) {
}
define i1 @test115(float %arg1, float %arg2, float %arg3, float %arg4, float %C) {
-; GFX11-LABEL: test115:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_dual_max_f32 v2, v2, v2 :: v_dual_max_f32 v1, v1, v1
-; GFX11-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v3, v3, v3
-; GFX11-NEXT: v_dual_min_f32 v0, v0, v1 :: v_dual_max_f32 v1, v2, v3
-; GFX11-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v4
-; GFX11-NEXT: v_cmp_nge_f32_e64 s0, v1, v4
-; GFX11-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11NONANS-LABEL: test115:
-; GFX11NONANS: ; %bb.0:
-; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT: v_max_f32_e32 v2, v2, v3
-; GFX11NONANS-NEXT: v_min3_f32 v0, v0, v1, v2
-; GFX11NONANS-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v4
-; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test115:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_dual_max_f32 v2, v2, v2 :: v_dual_max_f32 v3, v3, v3
+; CHECK-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v4
+; CHECK-NEXT: v_cmp_lt_f32_e64 s0, v1, v4
+; CHECK-NEXT: v_cmp_nge_f32_e64 s1, v2, v4
+; CHECK-NEXT: v_cmp_nge_f32_e64 s2, v3, v4
+; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0
+; CHECK-NEXT: s_and_b32 s1, s1, s2
+; CHECK-NEXT: s_or_b32 s0, s0, s1
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = fcmp olt float %arg1, %C
%cmp2 = fcmp olt float %arg2, %C
%var3 = call float @llvm.canonicalize.f32(float %arg3)
@@ -2268,44 +2094,30 @@ define i1 @test115(float %arg1, float %arg2, float %arg3, float %arg4, float %C)
}
define i1 @test116(float %arg1, float %arg2, float %arg3, float %arg4, float %arg5, float %arg6, float %arg7, float %arg8, float %arg9, float %arg10, float %C) {
-; GFX11-LABEL: test116:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_dual_max_f32 v9, v9, v9 :: v_dual_max_f32 v8, v8, v8
-; GFX11-NEXT: v_dual_max_f32 v1, v1, v1 :: v_dual_max_f32 v0, v0, v0
-; GFX11-NEXT: v_dual_max_f32 v3, v3, v3 :: v_dual_max_f32 v2, v2, v2
-; GFX11-NEXT: v_dual_max_f32 v5, v5, v5 :: v_dual_max_f32 v4, v4, v4
-; GFX11-NEXT: v_dual_max_f32 v7, v7, v7 :: v_dual_max_f32 v6, v6, v6
-; GFX11-NEXT: v_min_f32_e32 v8, v8, v9
-; GFX11-NEXT: v_dual_max_f32 v2, v2, v3 :: v_dual_min_f32 v3, v4, v5
-; GFX11-NEXT: v_max_f32_e32 v4, v6, v7
-; GFX11-NEXT: v_min3_f32 v0, v0, v1, v8
-; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, v2, v10
-; GFX11-NEXT: v_cmp_lt_f32_e64 s0, v3, v10
-; GFX11-NEXT: v_cmp_gt_f32_e64 s1, v4, v10
-; GFX11-NEXT: v_cmp_lt_f32_e64 s2, v0, v10
-; GFX11-NEXT: s_or_b32 s0, s0, s1
-; GFX11-NEXT: s_or_b32 s1, s2, vcc_lo
-; GFX11-NEXT: s_or_b32 s0, s0, s1
-; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11NONANS-LABEL: test116:
-; GFX11NONANS: ; %bb.0:
-; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT: v_min_f32_e32 v8, v8, v9
-; GFX11NONANS-NEXT: v_dual_max_f32 v2, v2, v3 :: v_dual_min_f32 v3, v4, v5
-; GFX11NONANS-NEXT: v_max_f32_e32 v4, v6, v7
-; GFX11NONANS-NEXT: v_min3_f32 v0, v0, v1, v8
-; GFX11NONANS-NEXT: v_cmp_gt_f32_e32 vcc_lo, v2, v10
-; GFX11NONANS-NEXT: v_cmp_lt_f32_e64 s0, v3, v10
-; GFX11NONANS-NEXT: v_cmp_gt_f32_e64 s1, v4, v10
-; GFX11NONANS-NEXT: v_cmp_lt_f32_e64 s2, v0, v10
-; GFX11NONANS-NEXT: s_or_b32 s0, s0, s1
-; GFX11NONANS-NEXT: s_or_b32 s1, s2, vcc_lo
-; GFX11NONANS-NEXT: s_or_b32 s0, s0, s1
-; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
-; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test116:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v10
+; CHECK-NEXT: v_cmp_lt_f32_e64 s0, v1, v10
+; CHECK-NEXT: v_cmp_gt_f32_e64 s1, v2, v10
+; CHECK-NEXT: v_cmp_gt_f32_e64 s2, v3, v10
+; CHECK-NEXT: v_cmp_lt_f32_e64 s3, v4, v10
+; CHECK-NEXT: v_cmp_lt_f32_e64 s4, v5, v10
+; CHECK-NEXT: v_cmp_gt_f32_e64 s5, v6, v10
+; CHECK-NEXT: v_cmp_gt_f32_e64 s6, v7, v10
+; CHECK-NEXT: v_cmp_lt_f32_e64 s7, v8, v10
+; CHECK-NEXT: v_cmp_lt_f32_e64 s8, v9, v10
+; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0
+; CHECK-NEXT: s_or_b32 s1, s1, s2
+; CHECK-NEXT: s_or_b32 s2, s3, s4
+; CHECK-NEXT: s_or_b32 s3, s5, s6
+; CHECK-NEXT: s_or_b32 s4, s7, s8
+; CHECK-NEXT: s_or_b32 s0, s0, s1
+; CHECK-NEXT: s_or_b32 s1, s2, s3
+; CHECK-NEXT: s_or_b32 s0, s4, s0
+; CHECK-NEXT: s_or_b32 s0, s1, s0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = fcmp olt float %arg1, %C
%cmp2 = fcmp olt float %arg2, %C
%cmp3 = fcmp ogt float %arg3, %C
@@ -2329,45 +2141,34 @@ define i1 @test116(float %arg1, float %arg2, float %arg3, float %arg4, float %ar
}
define i1 @test117(float %arg1, float %arg2, float %arg3, float %arg4, float %arg5, float %arg6, float %arg7, float %arg8, float %arg9, float %arg10, float %arg11, float %arg12, float %C1, float %C2) {
-; GFX11-LABEL: test117:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_dual_max_f32 v3, v3, v3 :: v_dual_max_f32 v6, v6, v6
-; GFX11-NEXT: v_dual_max_f32 v7, v7, v7 :: v_dual_max_f32 v10, v10, v10
-; GFX11-NEXT: v_dual_max_f32 v1, v1, v1 :: v_dual_max_f32 v0, v0, v0
-; GFX11-NEXT: v_dual_max_f32 v11, v11, v11 :: v_dual_max_f32 v2, v2, v2
-; GFX11-NEXT: v_min_f32_e32 v6, v6, v7
-; GFX11-NEXT: v_dual_min_f32 v0, v0, v1 :: v_dual_min_f32 v1, v10, v11
-; GFX11-NEXT: v_min_f32_e32 v2, v2, v3
-; GFX11-NEXT: v_min3_f32 v3, v4, v5, v6
-; GFX11-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v12
-; GFX11-NEXT: v_min3_f32 v0, v8, v9, v1
-; GFX11-NEXT: v_cmp_lt_f32_e64 s0, v2, v13
-; GFX11-NEXT: v_cmp_lt_f32_e64 s1, v3, v13
-; GFX11-NEXT: v_cmp_lt_f32_e64 s2, v0, v12
-; GFX11-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX11-NEXT: s_or_b32 s0, s0, s1
-; GFX11-NEXT: s_or_b32 s0, s2, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11NONANS-LABEL: test117:
-; GFX11NONANS: ; %bb.0:
-; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT: v_min_f32_e32 v6, v6, v7
-; GFX11NONANS-NEXT: v_dual_min_f32 v0, v0, v1 :: v_dual_min_f32 v1, v10, v11
-; GFX11NONANS-NEXT: v_min_f32_e32 v2, v2, v3
-; GFX11NONANS-NEXT: v_min3_f32 v3, v4, v5, v6
-; GFX11NONANS-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v12
-; GFX11NONANS-NEXT: v_min3_f32 v0, v8, v9, v1
-; GFX11NONANS-NEXT: v_cmp_lt_f32_e64 s0, v2, v13
-; GFX11NONANS-NEXT: v_cmp_lt_f32_e64 s1, v3, v13
-; GFX11NONANS-NEXT: v_cmp_lt_f32_e64 s2, v0, v12
-; GFX11NONANS-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX11NONANS-NEXT: s_or_b32 s0, s0, s1
-; GFX11NONANS-NEXT: s_or_b32 s0, s2, s0
-; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
-; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test117:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v12
+; CHECK-NEXT: v_cmp_lt_f32_e64 s0, v1, v12
+; CHECK-NEXT: v_cmp_lt_f32_e64 s1, v2, v13
+; CHECK-NEXT: v_cmp_lt_f32_e64 s2, v3, v13
+; CHECK-NEXT: v_cmp_lt_f32_e64 s3, v4, v13
+; CHECK-NEXT: v_cmp_lt_f32_e64 s4, v5, v13
+; CHECK-NEXT: v_cmp_lt_f32_e64 s5, v6, v13
+; CHECK-NEXT: v_cmp_lt_f32_e64 s6, v7, v13
+; CHECK-NEXT: v_cmp_lt_f32_e64 s7, v8, v12
+; CHECK-NEXT: v_cmp_lt_f32_e64 s8, v9, v12
+; CHECK-NEXT: v_cmp_lt_f32_e64 s9, v10, v12
+; CHECK-NEXT: v_cmp_lt_f32_e64 s10, v11, v12
+; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0
+; CHECK-NEXT: s_or_b32 s1, s1, s2
+; CHECK-NEXT: s_or_b32 s2, s3, s4
+; CHECK-NEXT: s_or_b32 s3, s5, s6
+; CHECK-NEXT: s_or_b32 s4, s7, s8
+; CHECK-NEXT: s_or_b32 s5, s9, s10
+; CHECK-NEXT: s_or_b32 s0, s0, s1
+; CHECK-NEXT: s_or_b32 s1, s2, s3
+; CHECK-NEXT: s_or_b32 s2, s4, s5
+; CHECK-NEXT: s_or_b32 s0, s0, s1
+; CHECK-NEXT: s_or_b32 s0, s2, s0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = fcmp olt float %arg1, %C1
%cmp2 = fcmp olt float %arg2, %C1
%cmp3 = fcmp olt float %arg3, %C2
@@ -2396,16 +2197,20 @@ define i1 @test117(float %arg1, float %arg2, float %arg3, float %arg4, float %ar
define i1 @test118(float %arg1, float %arg2, float %arg3, float %arg4, float %C1, float %C2, float %C3, float %C4, float %C) #0 {
-; GCN-LABEL: test118:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_dual_add_f32 v0, v0, v4 :: v_dual_add_f32 v1, v1, v5
-; GCN-NEXT: v_dual_add_f32 v2, v2, v6 :: v_dual_add_f32 v3, v3, v7
-; GCN-NEXT: v_min_f32_e32 v0, v0, v1
-; GCN-NEXT: v_max3_f32 v0, v0, v2, v3
-; GCN-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v8
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test118:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_dual_add_f32 v0, v0, v4 :: v_dual_add_f32 v1, v1, v5
+; CHECK-NEXT: v_dual_add_f32 v2, v2, v6 :: v_dual_add_f32 v3, v3, v7
+; CHECK-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v8
+; CHECK-NEXT: v_cmp_lt_f32_e64 s0, v1, v8
+; CHECK-NEXT: v_cmp_lt_f32_e64 s1, v2, v8
+; CHECK-NEXT: v_cmp_lt_f32_e64 s2, v3, v8
+; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0
+; CHECK-NEXT: s_and_b32 s1, s1, s2
+; CHECK-NEXT: s_and_b32 s0, s0, s1
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%add1 = fadd nnan float %arg1, %C1
%add2 = fadd nnan float %arg2, %C2
%add3 = fadd nnan float %arg3, %C3
@@ -2421,16 +2226,20 @@ define i1 @test118(float %arg1, float %arg2, float %arg3, float %arg4, float %C1
}
define i1 @test119(float %arg1, float %arg2, float %arg3, float %arg4, float %C1, float %C2, float %C3, float %C4, float %C) #0 {
-; GCN-LABEL: test119:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_dual_add_f32 v2, v2, v6 :: v_dual_add_f32 v3, v3, v7
-; GCN-NEXT: v_dual_add_f32 v0, v0, v4 :: v_dual_add_f32 v1, v1, v5
-; GCN-NEXT: v_min_f32_e32 v2, v2, v3
-; GCN-NEXT: v_minmax_f32 v0, v0, v1, v2
-; GCN-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v8
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test119:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_dual_add_f32 v0, v0, v4 :: v_dual_add_f32 v1, v1, v5
+; CHECK-NEXT: v_dual_add_f32 v2, v2, v6 :: v_dual_add_f32 v3, v3, v7
+; CHECK-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v8
+; CHECK-NEXT: v_cmp_lt_f32_e64 s0, v1, v8
+; CHECK-NEXT: v_cmp_lt_f32_e64 s1, v2, v8
+; CHECK-NEXT: v_cmp_lt_f32_e64 s2, v3, v8
+; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0
+; CHECK-NEXT: s_or_b32 s1, s1, s2
+; CHECK-NEXT: s_and_b32 s0, s0, s1
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%add1 = fadd nnan float %arg1, %C1
%add2 = fadd nnan float %arg2, %C2
%add3 = fadd nnan float %arg3, %C3
@@ -2446,16 +2255,20 @@ define i1 @test119(float %arg1, float %arg2, float %arg3, float %arg4, float %C1
}
define i1 @test120(float %arg1, float %arg2, float %arg3, float %arg4, float %C1, float %C2, float %C3, float %C4, float %C) #0 {
-; GCN-LABEL: test120:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_dual_add_f32 v2, v2, v6 :: v_dual_add_f32 v3, v3, v7
-; GCN-NEXT: v_dual_add_f32 v0, v0, v4 :: v_dual_add_f32 v1, v1, v5
-; GCN-NEXT: v_max_f32_e32 v2, v2, v3
-; GCN-NEXT: v_min3_f32 v0, v0, v1, v2
-; GCN-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v8
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test120:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_dual_add_f32 v0, v0, v4 :: v_dual_add_f32 v1, v1, v5
+; CHECK-NEXT: v_dual_add_f32 v2, v2, v6 :: v_dual_add_f32 v3, v3, v7
+; CHECK-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v8
+; CHECK-NEXT: v_cmp_lt_f32_e64 s0, v1, v8
+; CHECK-NEXT: v_cmp_lt_f32_e64 s1, v2, v8
+; CHECK-NEXT: v_cmp_lt_f32_e64 s2, v3, v8
+; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0
+; CHECK-NEXT: s_and_b32 s1, s1, s2
+; CHECK-NEXT: s_or_b32 s0, s0, s1
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%add1 = fadd nnan float %arg1, %C1
%add2 = fadd nnan float %arg2, %C2
%add3 = fadd nnan float %arg3, %C3
@@ -2471,16 +2284,20 @@ define i1 @test120(float %arg1, float %arg2, float %arg3, float %arg4, float %C1
}
define i1 @test121(float %arg1, float %arg2, float %arg3, float %arg4, float %C1, float %C2, float %C3, float %C4, float %C) #0 {
-; GCN-LABEL: test121:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_dual_add_f32 v2, v2, v6 :: v_dual_add_f32 v3, v3, v7
-; GCN-NEXT: v_dual_add_f32 v0, v0, v4 :: v_dual_add_f32 v1, v1, v5
-; GCN-NEXT: v_max_f32_e32 v2, v2, v3
-; GCN-NEXT: v_maxmin_f32 v0, v0, v1, v2
-; GCN-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v8
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: test121:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_dual_add_f32 v0, v0, v4 :: v_dual_add_f32 v1, v1, v5
+; CHECK-NEXT: v_dual_add_f32 v2, v2, v6 :: v_dual_add_f32 v3, v3, v7
+; CHECK-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v8
+; CHECK-NEXT: v_cmp_lt_f32_e64 s0, v1, v8
+; CHECK-NEXT: v_cmp_lt_f32_e64 s1, v2, v8
+; CHECK-NEXT: v_cmp_lt_f32_e64 s2, v3, v8
+; CHECK-NEXT: s_and_b32 s0, vcc_lo, s0
+; CHECK-NEXT: s_and_b32 s1, s1, s2
+; CHECK-NEXT: s_or_b32 s0, s0, s1
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%add1 = fadd nnan float %arg1, %C1
%add2 = fadd nnan float %arg2, %C2
%add3 = fadd nnan float %arg3, %C3
@@ -2495,173 +2312,141 @@ define i1 @test121(float %arg1, float %arg2, float %arg3, float %arg4, float %C1
ret i1 %and2
}
-define i1 @test122(double %arg1, double %arg2, double %arg3) #1 {
-; GCN-LABEL: test122:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3]
-; GCN-NEXT: v_cmp_lt_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
- %cmp1 = fcmp ult double %arg1, %arg3
- %cmp2 = fcmp ult double %arg2, %arg3
- %or1 = or i1 %cmp1, %cmp2
- ret i1 %or1
-}
-
-define i1 @test123(double %arg1, double %arg2, double %arg3) #1 {
-; GCN-LABEL: test123:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]
-; GCN-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
-; GCN-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3]
-; GCN-NEXT: v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-NEXT: s_setpc_b64 s[30:31]
- %var1 = call double @llvm.canonicalize.f64(double %arg1)
- %var2 = call double @llvm.canonicalize.f64(double %arg2)
- %cmp1 = fcmp ogt double %var1, %arg3
- %cmp2 = fcmp ogt double %var2, %arg3
- %or1 = and i1 %cmp1, %cmp2
- ret i1 %or1
-}
-
; The optimization does not apply to the following tests.
-define i1 @test124(i32 %arg1, i64 %arg2) {
-; GCN-LABEL: test124:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: s_mov_b64 s[0:1], 0x3e8
-; GCN-NEXT: v_cmp_gt_i64_e32 vcc_lo, s[0:1], v[1:2]
-; GCN-NEXT: v_cmp_gt_i32_e64 s0, 0x3e8, v0
-; GCN-NEXT: s_or_b32 s0, s0, vcc_lo
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
-; GCN-NEXT: s_setpc_b64 s[30:31]
+define i1 @test122(i32 %arg1, i64 %arg2) {
+; CHECK-LABEL: test122:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: s_mov_b64 s[0:1], 0x3e8
+; CHECK-NEXT: v_cmp_gt_i64_e32 vcc_lo, s[0:1], v[1:2]
+; CHECK-NEXT: v_cmp_gt_i32_e64 s0, 0x3e8, v0
+; CHECK-NEXT: s_or_b32 s0, s0, vcc_lo
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp slt i32 %arg1, 1000
%cmp2 = icmp slt i64 %arg2, 1000
%or = or i1 %cmp1, %cmp2
ret i1 %or
}
-define i1 @test125(i32 %arg1, i32 %arg2) {
-; GCN-LABEL: test125:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0x3e8, v0
-; GCN-NEXT: v_cmp_eq_u32_e64 s0, 0x3e8, v1
-; GCN-NEXT: s_or_b32 s0, vcc_lo, s0
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
-; GCN-NEXT: s_setpc_b64 s[30:31]
+define i1 @test123(i32 %arg1, i32 %arg2) {
+; CHECK-LABEL: test123:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0x3e8, v0
+; CHECK-NEXT: v_cmp_eq_u32_e64 s0, 0x3e8, v1
+; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp eq i32 %arg1, 1000
%cmp2 = icmp eq i32 %arg2, 1000
%or = or i1 %cmp1, %cmp2
ret i1 %or
}
-define i1 @test126(i32 %arg1, i32 %arg2) {
-; GCN-LABEL: test126:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0x3e8, v0
-; GCN-NEXT: v_cmp_ne_u32_e64 s0, 0x3e8, v1
-; GCN-NEXT: s_or_b32 s0, vcc_lo, s0
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
-; GCN-NEXT: s_setpc_b64 s[30:31]
+define i1 @test124(i32 %arg1, i32 %arg2) {
+; CHECK-LABEL: test124:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0x3e8, v0
+; CHECK-NEXT: v_cmp_ne_u32_e64 s0, 0x3e8, v1
+; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp ne i32 %arg1, 1000
%cmp2 = icmp ne i32 %arg2, 1000
%or = or i1 %cmp1, %cmp2
ret i1 %or
}
-define i1 @test127(i64 %arg1, i64 %arg2, i64 %arg3) {
-; GCN-LABEL: test127:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[4:5]
-; GCN-NEXT: v_cmp_lt_u64_e64 s0, v[2:3], v[4:5]
-; GCN-NEXT: s_or_b32 s0, vcc_lo, s0
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
-; GCN-NEXT: s_setpc_b64 s[30:31]
+define i1 @test125(i64 %arg1, i64 %arg2, i64 %arg3) {
+; CHECK-LABEL: test125:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[4:5]
+; CHECK-NEXT: v_cmp_lt_u64_e64 s0, v[2:3], v[4:5]
+; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp ult i64 %arg1, %arg3
%cmp2 = icmp ult i64 %arg2, %arg3
%or = or i1 %cmp1, %cmp2
ret i1 %or
}
-define i1 @test128(i32 %arg1, i32 %arg2, i32 %arg3) {
-; GCN-LABEL: test128:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_cmp_lt_u32_e32 vcc_lo, v0, v2
-; GCN-NEXT: v_cmp_lt_u32_e64 s0, v2, v1
-; GCN-NEXT: s_or_b32 s0, vcc_lo, s0
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
-; GCN-NEXT: s_setpc_b64 s[30:31]
+define i1 @test126(i32 %arg1, i32 %arg2, i32 %arg3) {
+; CHECK-LABEL: test126:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_cmp_lt_u32_e32 vcc_lo, v0, v2
+; CHECK-NEXT: v_cmp_lt_u32_e64 s0, v2, v1
+; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp ult i32 %arg1, %arg3
%cmp2 = icmp ult i32 %arg3, %arg2
%or = or i1 %cmp1, %cmp2
ret i1 %or
}
-define i1 @test129(i32 %arg1, i32 %arg2, i32 %arg3) {
-; GCN-LABEL: test129:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_cmp_lt_u32_e32 vcc_lo, v0, v2
-; GCN-NEXT: v_cmp_le_u32_e64 s0, v1, v2
-; GCN-NEXT: s_or_b32 s0, vcc_lo, s0
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
-; GCN-NEXT: s_setpc_b64 s[30:31]
+define i1 @test127(i32 %arg1, i32 %arg2, i32 %arg3) {
+; CHECK-LABEL: test127:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_cmp_lt_u32_e32 vcc_lo, v0, v2
+; CHECK-NEXT: v_cmp_le_u32_e64 s0, v1, v2
+; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp ult i32 %arg1, %arg3
%cmp2 = icmp ule i32 %arg2, %arg3
%or = or i1 %cmp1, %cmp2
ret i1 %or
}
-define i1 @test130(i32 %arg1, i32 %arg2, i32 %arg3) {
-; GCN-LABEL: test130:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_cmp_le_u32_e32 vcc_lo, v2, v0
-; GCN-NEXT: v_cmp_gt_u32_e64 s0, v1, v2
-; GCN-NEXT: s_or_b32 s0, vcc_lo, s0
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
-; GCN-NEXT: s_setpc_b64 s[30:31]
+define i1 @test128(i32 %arg1, i32 %arg2, i32 %arg3) {
+; CHECK-LABEL: test128:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_cmp_le_u32_e32 vcc_lo, v2, v0
+; CHECK-NEXT: v_cmp_gt_u32_e64 s0, v1, v2
+; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp ule i32 %arg3, %arg1
%cmp2 = icmp ugt i32 %arg2, %arg3
%or = or i1 %cmp1, %cmp2
ret i1 %or
}
-define i1 @test131(i16 %arg1, i32 %arg2) {
-; GCN-LABEL: test131:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_cmp_gt_u16_e32 vcc_lo, 10, v0
-; GCN-NEXT: v_cmp_gt_u32_e64 s0, 10, v1
-; GCN-NEXT: s_or_b32 s0, vcc_lo, s0
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
-; GCN-NEXT: s_setpc_b64 s[30:31]
+define i1 @test129(i16 %arg1, i32 %arg2) {
+; CHECK-LABEL: test129:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_cmp_gt_u16_e32 vcc_lo, 10, v0
+; CHECK-NEXT: v_cmp_gt_u32_e64 s0, 10, v1
+; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp ult i16 %arg1, 10
%cmp2 = icmp ult i32 %arg2, 10
%or = or i1 %cmp1, %cmp2
ret i1 %or
}
-define i1 @test132(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4) {
-; GCN-LABEL: test132:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_cmp_lt_u32_e32 vcc_lo, v0, v2
-; GCN-NEXT: v_cmp_lt_u32_e64 s0, v1, v2
-; GCN-NEXT: v_cmp_lt_u32_e64 s1, v0, v3
-; GCN-NEXT: s_or_b32 s0, vcc_lo, s0
-; GCN-NEXT: s_or_b32 s1, s1, vcc_lo
-; GCN-NEXT: s_or_b32 s0, s0, s1
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
-; GCN-NEXT: s_setpc_b64 s[30:31]
+define i1 @test130(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4) {
+; CHECK-LABEL: test130:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_cmp_lt_u32_e32 vcc_lo, v0, v2
+; CHECK-NEXT: v_cmp_lt_u32_e64 s0, v1, v2
+; CHECK-NEXT: v_cmp_lt_u32_e64 s1, v0, v3
+; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0
+; CHECK-NEXT: s_or_b32 s1, s1, vcc_lo
+; CHECK-NEXT: s_or_b32 s0, s0, s1
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp ult i32 %arg1, %arg3
%cmp2 = icmp ult i32 %arg2, %arg3
%or1 = or i1 %cmp1, %cmp2
@@ -2671,88 +2456,62 @@ define i1 @test132(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4) {
ret i1 %or3
}
-define i1 @test133(i32 %arg1, i32 %arg2) {
-; GCN-LABEL: test133:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_cmp_gt_u32_e32 vcc_lo, 0x64, v0
-; GCN-NEXT: v_cmp_gt_u32_e64 s0, 0x3e8, v1
-; GCN-NEXT: s_or_b32 s0, vcc_lo, s0
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
-; GCN-NEXT: s_setpc_b64 s[30:31]
+define i1 @test131(i32 %arg1, i32 %arg2) {
+; CHECK-LABEL: test131:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_cmp_gt_u32_e32 vcc_lo, 0x64, v0
+; CHECK-NEXT: v_cmp_gt_u32_e64 s0, 0x3e8, v1
+; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = icmp ult i32 %arg1, 100
%cmp2 = icmp ult i32 %arg2, 1000
%or = or i1 %cmp1, %cmp2
ret i1 %or
}
-define i1 @test134(float %arg1, float %arg2, float %arg3) #0 {
-; GFX11-LABEL: test134:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v2
-; GFX11-NEXT: v_cmp_gt_f32_e64 s0, v2, v1
-; GFX11-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11NONANS-LABEL: test134:
-; GFX11NONANS: ; %bb.0:
-; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT: v_max_f32_e32 v0, v0, v1
-; GFX11NONANS-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v2
-; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]
+define i1 @test132(float %arg1, float %arg2, float %arg3) #0 {
+; CHECK-LABEL: test132:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v2
+; CHECK-NEXT: v_cmp_gt_f32_e64 s0, v2, v1
+; CHECK-NEXT: s_and_b32 s0, vcc_lo, s0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = fcmp olt float %arg1, %arg3
%cmp2 = fcmp ogt float %arg3, %arg2
%and1 = and i1 %cmp1, %cmp2
ret i1 %and1
}
-define i1 @test135(float %arg1, float %arg2, float %arg3) #0 {
-; GFX11-LABEL: test135:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_cmp_nge_f32_e32 vcc_lo, v0, v2
-; GFX11-NEXT: v_cmp_nle_f32_e64 s0, v2, v1
-; GFX11-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11NONANS-LABEL: test135:
-; GFX11NONANS: ; %bb.0:
-; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT: v_min_f32_e32 v0, v0, v1
-; GFX11NONANS-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v2
-; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]
+define i1 @test133(float %arg1, float %arg2, float %arg3) #0 {
+; CHECK-LABEL: test133:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_cmp_nge_f32_e32 vcc_lo, v0, v2
+; CHECK-NEXT: v_cmp_nle_f32_e64 s0, v2, v1
+; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = fcmp ult float %arg1, %arg3
%cmp2 = fcmp ugt float %arg3, %arg2
%or1 = or i1 %cmp1, %cmp2
ret i1 %or1
}
-define i1 @test136(double %arg1, double %arg2, double %arg3) {
-; GFX11-LABEL: test136:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]
-; GFX11-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
-; GFX11-NEXT: v_cmp_le_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX11-NEXT: v_cmp_ge_f64_e64 s0, v[4:5], v[2:3]
-; GFX11-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11NONANS-LABEL: test136:
-; GFX11NONANS: ; %bb.0:
-; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]
-; GFX11NONANS-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
-; GFX11NONANS-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3]
-; GFX11NONANS-NEXT: v_cmp_le_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]
+define i1 @test134(double %arg1, double %arg2, double %arg3) {
+; CHECK-LABEL: test134:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]
+; CHECK-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
+; CHECK-NEXT: v_cmp_le_f64_e32 vcc_lo, v[0:1], v[4:5]
+; CHECK-NEXT: v_cmp_ge_f64_e64 s0, v[4:5], v[2:3]
+; CHECK-NEXT: s_and_b32 s0, vcc_lo, s0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%var1 = call double @llvm.canonicalize.f64(double %arg1)
%var2 = call double @llvm.canonicalize.f64(double %arg2)
%cmp1 = fcmp ole double %var1, %arg3
@@ -2761,24 +2520,16 @@ define i1 @test136(double %arg1, double %arg2, double %arg3) {
ret i1 %and1
}
-define i1 @test137(float %arg1, float %arg2, float %arg3) {
-; GFX11-LABEL: test137:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1
-; GFX11-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v0, v2
-; GFX11-NEXT: v_cmp_nlt_f32_e64 s0, v2, v1
-; GFX11-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11NONANS-LABEL: test137:
-; GFX11NONANS: ; %bb.0:
-; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT: v_min_f32_e32 v0, v0, v1
-; GFX11NONANS-NEXT: v_cmp_le_f32_e32 vcc_lo, v0, v2
-; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]
+define i1 @test135(float %arg1, float %arg2, float %arg3) {
+; CHECK-LABEL: test135:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1
+; CHECK-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v0, v2
+; CHECK-NEXT: v_cmp_nlt_f32_e64 s0, v2, v1
+; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%var1 = call float @llvm.canonicalize.f32(float %arg1)
%var2 = call float @llvm.canonicalize.f32(float %arg2)
%cmp1 = fcmp ule float %var1, %arg3
@@ -2787,208 +2538,136 @@ define i1 @test137(float %arg1, float %arg2, float %arg3) {
ret i1 %or1
}
-define i1 @test138(float %arg1, float %arg2, float %arg3) #0 {
-; GFX11-LABEL: test138:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v2
-; GFX11-NEXT: v_cmp_lt_f32_e64 s0, v1, v2
-; GFX11-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11NONANS-LABEL: test138:
-; GFX11NONANS: ; %bb.0:
-; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT: v_max_f32_e32 v0, v0, v1
-; GFX11NONANS-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v2
-; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]
+define i1 @test136(float %arg1, float %arg2, float %arg3) #0 {
+; CHECK-LABEL: test136:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v2
+; CHECK-NEXT: v_cmp_lt_f32_e64 s0, v1, v2
+; CHECK-NEXT: s_and_b32 s0, vcc_lo, s0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = fcmp olt float %arg1, %arg3
%cmp2 = fcmp olt float %arg2, %arg3
%and1 = and i1 %cmp1, %cmp2
ret i1 %and1
}
-define i1 @test139(double %arg1, double %arg2, double %arg3) #0 {
-; GFX11-LABEL: test139:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_cmp_le_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX11-NEXT: v_cmp_le_f64_e64 s0, v[2:3], v[4:5]
-; GFX11-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11NONANS-LABEL: test139:
-; GFX11NONANS: ; %bb.0:
-; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3]
-; GFX11NONANS-NEXT: v_cmp_le_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]
+define i1 @test137(double %arg1, double %arg2, double %arg3) #0 {
+; CHECK-LABEL: test137:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_cmp_le_f64_e32 vcc_lo, v[0:1], v[4:5]
+; CHECK-NEXT: v_cmp_le_f64_e64 s0, v[2:3], v[4:5]
+; CHECK-NEXT: s_and_b32 s0, vcc_lo, s0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = fcmp ole double %arg1, %arg3
%cmp2 = fcmp ole double %arg2, %arg3
%and1 = and i1 %cmp1, %cmp2
ret i1 %and1
}
-define i1 @test140(double %arg1, double %arg2, double %arg3) #0 {
-; GFX11-LABEL: test140:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX11-NEXT: v_cmp_gt_f64_e64 s0, v[2:3], v[4:5]
-; GFX11-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11NONANS-LABEL: test140:
-; GFX11NONANS: ; %bb.0:
-; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3]
-; GFX11NONANS-NEXT: v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]
+define i1 @test138(double %arg1, double %arg2, double %arg3) #0 {
+; CHECK-LABEL: test138:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]
+; CHECK-NEXT: v_cmp_gt_f64_e64 s0, v[2:3], v[4:5]
+; CHECK-NEXT: s_and_b32 s0, vcc_lo, s0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = fcmp ogt double %arg1, %arg3
%cmp2 = fcmp ogt double %arg2, %arg3
%and1 = and i1 %cmp1, %cmp2
ret i1 %and1
}
-define i1 @test141(float %arg1, float %arg2, float %arg3) #0 {
-; GFX11-LABEL: test141:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_cmp_ge_f32_e32 vcc_lo, v0, v2
-; GFX11-NEXT: v_cmp_ge_f32_e64 s0, v1, v2
-; GFX11-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11NONANS-LABEL: test141:
-; GFX11NONANS: ; %bb.0:
-; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT: v_min_f32_e32 v0, v0, v1
-; GFX11NONANS-NEXT: v_cmp_ge_f32_e32 vcc_lo, v0, v2
-; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]
+define i1 @test139(float %arg1, float %arg2, float %arg3) #0 {
+; CHECK-LABEL: test139:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_cmp_ge_f32_e32 vcc_lo, v0, v2
+; CHECK-NEXT: v_cmp_ge_f32_e64 s0, v1, v2
+; CHECK-NEXT: s_and_b32 s0, vcc_lo, s0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = fcmp oge float %arg1, %arg3
%cmp2 = fcmp oge float %arg2, %arg3
%and1 = and i1 %cmp1, %cmp2
ret i1 %and1
}
-define i1 @test142(double %arg1, double %arg2, double %arg3) #0 {
-; GFX11-LABEL: test142:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_cmp_nle_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX11-NEXT: v_cmp_nle_f64_e64 s0, v[2:3], v[4:5]
-; GFX11-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11NONANS-LABEL: test142:
-; GFX11NONANS: ; %bb.0:
-; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3]
-; GFX11NONANS-NEXT: v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]
+define i1 @test140(double %arg1, double %arg2, double %arg3) #0 {
+; CHECK-LABEL: test140:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_cmp_nle_f64_e32 vcc_lo, v[0:1], v[4:5]
+; CHECK-NEXT: v_cmp_nle_f64_e64 s0, v[2:3], v[4:5]
+; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = fcmp ugt double %arg1, %arg3
%cmp2 = fcmp ugt double %arg2, %arg3
%or1 = or i1 %cmp1, %cmp2
ret i1 %or1
}
-define i1 @test143(float %arg1, float %arg2, float %arg3) #0 {
-; GFX11-LABEL: test143:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_cmp_nlt_f32_e32 vcc_lo, v0, v2
-; GFX11-NEXT: v_cmp_nlt_f32_e64 s0, v1, v2
-; GFX11-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11NONANS-LABEL: test143:
-; GFX11NONANS: ; %bb.0:
-; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT: v_max_f32_e32 v0, v0, v1
-; GFX11NONANS-NEXT: v_cmp_ge_f32_e32 vcc_lo, v0, v2
-; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]
+define i1 @test141(float %arg1, float %arg2, float %arg3) #0 {
+; CHECK-LABEL: test141:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_cmp_nlt_f32_e32 vcc_lo, v0, v2
+; CHECK-NEXT: v_cmp_nlt_f32_e64 s0, v1, v2
+; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = fcmp uge float %arg1, %arg3
%cmp2 = fcmp uge float %arg2, %arg3
%or1 = or i1 %cmp1, %cmp2
ret i1 %or1
}
-define i1 @test144(float %arg1, float %arg2, float %arg3) #0 {
-; GFX11-LABEL: test144:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v0, v2
-; GFX11-NEXT: v_cmp_ngt_f32_e64 s0, v1, v2
-; GFX11-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11NONANS-LABEL: test144:
-; GFX11NONANS: ; %bb.0:
-; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT: v_min_f32_e32 v0, v0, v1
-; GFX11NONANS-NEXT: v_cmp_le_f32_e32 vcc_lo, v0, v2
-; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]
+define i1 @test142(float %arg1, float %arg2, float %arg3) #0 {
+; CHECK-LABEL: test142:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v0, v2
+; CHECK-NEXT: v_cmp_ngt_f32_e64 s0, v1, v2
+; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = fcmp ule float %arg1, %arg3
%cmp2 = fcmp ule float %arg2, %arg3
%or1 = or i1 %cmp1, %cmp2
ret i1 %or1
}
-define i1 @test145(double %arg1, double %arg2, double %arg3) #0 {
-; GFX11-LABEL: test145:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_cmp_nge_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX11-NEXT: v_cmp_nge_f64_e64 s0, v[2:3], v[4:5]
-; GFX11-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11NONANS-LABEL: test145:
-; GFX11NONANS: ; %bb.0:
-; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3]
-; GFX11NONANS-NEXT: v_cmp_lt_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]
+define i1 @test143(double %arg1, double %arg2, double %arg3) #0 {
+; CHECK-LABEL: test143:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_cmp_nge_f64_e32 vcc_lo, v[0:1], v[4:5]
+; CHECK-NEXT: v_cmp_nge_f64_e64 s0, v[2:3], v[4:5]
+; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%cmp1 = fcmp ult double %arg1, %arg3
%cmp2 = fcmp ult double %arg2, %arg3
%or1 = or i1 %cmp1, %cmp2
ret i1 %or1
}
-define i1 @test146(float %arg1, float %arg2, float %arg3) {
-; GFX11-LABEL: test146:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1
-; GFX11-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v2
-; GFX11-NEXT: v_cmp_lt_f32_e64 s0, v1, v2
-; GFX11-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11NONANS-LABEL: test146:
-; GFX11NONANS: ; %bb.0:
-; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT: v_max_f32_e32 v0, v0, v1
-; GFX11NONANS-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v2
-; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]
+define i1 @test144(float %arg1, float %arg2, float %arg3) {
+; CHECK-LABEL: test144:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1
+; CHECK-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v2
+; CHECK-NEXT: v_cmp_lt_f32_e64 s0, v1, v2
+; CHECK-NEXT: s_and_b32 s0, vcc_lo, s0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%var1 = call float @llvm.canonicalize.f32(float %arg1)
%var2 = call float @llvm.canonicalize.f32(float %arg2)
%cmp1 = fcmp olt float %var1, %arg3
@@ -2997,27 +2676,17 @@ define i1 @test146(float %arg1, float %arg2, float %arg3) {
ret i1 %and1
}
-define i1 @test147(double %arg1, double %arg2, double %arg3) {
-; GFX11-LABEL: test147:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]
-; GFX11-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
-; GFX11-NEXT: v_cmp_le_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX11-NEXT: v_cmp_le_f64_e64 s0, v[2:3], v[4:5]
-; GFX11-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11NONANS-LABEL: test147:
-; GFX11NONANS: ; %bb.0:
-; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]
-; GFX11NONANS-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
-; GFX11NONANS-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3]
-; GFX11NONANS-NEXT: v_cmp_le_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]
+define i1 @test145(double %arg1, double %arg2, double %arg3) {
+; CHECK-LABEL: test145:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]
+; CHECK-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
+; CHECK-NEXT: v_cmp_le_f64_e32 vcc_lo, v[0:1], v[4:5]
+; CHECK-NEXT: v_cmp_le_f64_e64 s0, v[2:3], v[4:5]
+; CHECK-NEXT: s_and_b32 s0, vcc_lo, s0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%var1 = call double @llvm.canonicalize.f64(double %arg1)
%var2 = call double @llvm.canonicalize.f64(double %arg2)
%cmp1 = fcmp ole double %var1, %arg3
@@ -3026,27 +2695,17 @@ define i1 @test147(double %arg1, double %arg2, double %arg3) {
ret i1 %and1
}
-define i1 @test148(double %arg1, double %arg2, double %arg3) {
-; GFX11-LABEL: test148:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]
-; GFX11-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
-; GFX11-NEXT: v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX11-NEXT: v_cmp_gt_f64_e64 s0, v[2:3], v[4:5]
-; GFX11-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11NONANS-LABEL: test148:
-; GFX11NONANS: ; %bb.0:
-; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]
-; GFX11NONANS-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
-; GFX11NONANS-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3]
-; GFX11NONANS-NEXT: v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]
+define i1 @test146(double %arg1, double %arg2, double %arg3) {
+; CHECK-LABEL: test146:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]
+; CHECK-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
+; CHECK-NEXT: v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]
+; CHECK-NEXT: v_cmp_gt_f64_e64 s0, v[2:3], v[4:5]
+; CHECK-NEXT: s_and_b32 s0, vcc_lo, s0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%var1 = call double @llvm.canonicalize.f64(double %arg1)
%var2 = call double @llvm.canonicalize.f64(double %arg2)
%cmp1 = fcmp ogt double %var1, %arg3
@@ -3055,24 +2714,16 @@ define i1 @test148(double %arg1, double %arg2, double %arg3) {
ret i1 %and1
}
-define i1 @test149(float %arg1, float %arg2, float %arg3) {
-; GFX11-LABEL: test149:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1
-; GFX11-NEXT: v_cmp_ge_f32_e32 vcc_lo, v0, v2
-; GFX11-NEXT: v_cmp_ge_f32_e64 s0, v1, v2
-; GFX11-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11NONANS-LABEL: test149:
-; GFX11NONANS: ; %bb.0:
-; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT: v_min_f32_e32 v0, v0, v1
-; GFX11NONANS-NEXT: v_cmp_ge_f32_e32 vcc_lo, v0, v2
-; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]
+define i1 @test147(float %arg1, float %arg2, float %arg3) {
+; CHECK-LABEL: test147:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1
+; CHECK-NEXT: v_cmp_ge_f32_e32 vcc_lo, v0, v2
+; CHECK-NEXT: v_cmp_ge_f32_e64 s0, v1, v2
+; CHECK-NEXT: s_and_b32 s0, vcc_lo, s0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%var1 = call float @llvm.canonicalize.f32(float %arg1)
%var2 = call float @llvm.canonicalize.f32(float %arg2)
%cmp1 = fcmp oge float %var1, %arg3
@@ -3081,27 +2732,17 @@ define i1 @test149(float %arg1, float %arg2, float %arg3) {
ret i1 %and1
}
-define i1 @test150(double %arg1, double %arg2, double %arg3) {
-; GFX11-LABEL: test150:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]
-; GFX11-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
-; GFX11-NEXT: v_cmp_nle_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX11-NEXT: v_cmp_nle_f64_e64 s0, v[2:3], v[4:5]
-; GFX11-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11NONANS-LABEL: test150:
-; GFX11NONANS: ; %bb.0:
-; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]
-; GFX11NONANS-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
-; GFX11NONANS-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3]
-; GFX11NONANS-NEXT: v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]
+define i1 @test148(double %arg1, double %arg2, double %arg3) {
+; CHECK-LABEL: test148:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]
+; CHECK-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
+; CHECK-NEXT: v_cmp_nle_f64_e32 vcc_lo, v[0:1], v[4:5]
+; CHECK-NEXT: v_cmp_nle_f64_e64 s0, v[2:3], v[4:5]
+; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%var1 = call double @llvm.canonicalize.f64(double %arg1)
%var2 = call double @llvm.canonicalize.f64(double %arg2)
%cmp1 = fcmp ugt double %var1, %arg3
@@ -3110,24 +2751,16 @@ define i1 @test150(double %arg1, double %arg2, double %arg3) {
ret i1 %or1
}
-define i1 @test151(float %arg1, float %arg2, float %arg3) {
-; GFX11-LABEL: test151:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1
-; GFX11-NEXT: v_cmp_nlt_f32_e32 vcc_lo, v0, v2
-; GFX11-NEXT: v_cmp_nlt_f32_e64 s0, v1, v2
-; GFX11-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11NONANS-LABEL: test151:
-; GFX11NONANS: ; %bb.0:
-; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT: v_max_f32_e32 v0, v0, v1
-; GFX11NONANS-NEXT: v_cmp_ge_f32_e32 vcc_lo, v0, v2
-; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]
+define i1 @test149(float %arg1, float %arg2, float %arg3) {
+; CHECK-LABEL: test149:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1
+; CHECK-NEXT: v_cmp_nlt_f32_e32 vcc_lo, v0, v2
+; CHECK-NEXT: v_cmp_nlt_f32_e64 s0, v1, v2
+; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%var1 = call float @llvm.canonicalize.f32(float %arg1)
%var2 = call float @llvm.canonicalize.f32(float %arg2)
%cmp1 = fcmp uge float %var1, %arg3
@@ -3136,24 +2769,16 @@ define i1 @test151(float %arg1, float %arg2, float %arg3) {
ret i1 %or1
}
-define i1 @test152(float %arg1, float %arg2, float %arg3) {
-; GFX11-LABEL: test152:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1
-; GFX11-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v0, v2
-; GFX11-NEXT: v_cmp_ngt_f32_e64 s0, v1, v2
-; GFX11-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11NONANS-LABEL: test152:
-; GFX11NONANS: ; %bb.0:
-; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT: v_min_f32_e32 v0, v0, v1
-; GFX11NONANS-NEXT: v_cmp_le_f32_e32 vcc_lo, v0, v2
-; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]
+define i1 @test150(float %arg1, float %arg2, float %arg3) {
+; CHECK-LABEL: test150:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1
+; CHECK-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v0, v2
+; CHECK-NEXT: v_cmp_ngt_f32_e64 s0, v1, v2
+; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%var1 = call float @llvm.canonicalize.f32(float %arg1)
%var2 = call float @llvm.canonicalize.f32(float %arg2)
%cmp1 = fcmp ule float %var1, %arg3
@@ -3162,27 +2787,17 @@ define i1 @test152(float %arg1, float %arg2, float %arg3) {
ret i1 %or1
}
-define i1 @test153(double %arg1, double %arg2, double %arg3) {
-; GFX11-LABEL: test153:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]
-; GFX11-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
-; GFX11-NEXT: v_cmp_nge_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX11-NEXT: v_cmp_nge_f64_e64 s0, v[2:3], v[4:5]
-; GFX11-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11NONANS-LABEL: test153:
-; GFX11NONANS: ; %bb.0:
-; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]
-; GFX11NONANS-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
-; GFX11NONANS-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3]
-; GFX11NONANS-NEXT: v_cmp_lt_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT: s_setpc_b64 s[30:31]
+define i1 @test151(double %arg1, double %arg2, double %arg3) {
+; CHECK-LABEL: test151:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]
+; CHECK-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
+; CHECK-NEXT: v_cmp_nge_f64_e32 vcc_lo, v[0:1], v[4:5]
+; CHECK-NEXT: v_cmp_nge_f64_e64 s0, v[2:3], v[4:5]
+; CHECK-NEXT: s_or_b32 s0, vcc_lo, s0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%var1 = call double @llvm.canonicalize.f64(double %arg1)
%var2 = call double @llvm.canonicalize.f64(double %arg2)
%cmp1 = fcmp ult double %var1, %arg3
@@ -3197,4 +2812,3 @@ declare half @llvm.canonicalize.f16(half)
declare <2 x half> @llvm.canonicalize.v2f16(<2 x half>)
attributes #0 = { nounwind "amdgpu-ieee"="false" }
-attributes #1 = { nounwind "unsafe-fp-math"="true" "no-nans-fp-math"="true" }
diff --git a/llvm/test/CodeGen/AMDGPU/fma.f16.ll b/llvm/test/CodeGen/AMDGPU/fma.f16.ll
index 23971f2b681cb0..a9db224fc843b2 100644
--- a/llvm/test/CodeGen/AMDGPU/fma.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fma.f16.ll
@@ -92,30 +92,18 @@ define half @test_fmamk(half %x, half %y, half %z) {
; Regression test for a crash caused by D139469.
define i32 @test_D139469_f16(half %arg) {
-; GFX9-SDAG-LABEL: test_D139469_f16:
-; GFX9-SDAG: ; %bb.0: ; %bb
-; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SDAG-NEXT: s_movk_i32 s4, 0x291e
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, 0x211e
-; GFX9-SDAG-NEXT: v_mul_f16_e32 v1, 0x291e, v0
-; GFX9-SDAG-NEXT: v_fma_f16 v0, v0, s4, v2
-; GFX9-SDAG-NEXT: v_min_f16_e32 v0, v1, v0
-; GFX9-SDAG-NEXT: v_cmp_gt_f16_e32 vcc, 0, v0
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-GISEL-LABEL: test_D139469_f16:
-; GFX9-GISEL: ; %bb.0: ; %bb
-; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_mul_f16_e32 v1, 0x291e, v0
-; GFX9-GISEL-NEXT: s_movk_i32 s4, 0x291e
-; GFX9-GISEL-NEXT: v_cmp_gt_f16_e32 vcc, 0, v1
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, 0x211e
-; GFX9-GISEL-NEXT: v_fma_f16 v0, v0, s4, v1
-; GFX9-GISEL-NEXT: v_cmp_gt_f16_e64 s[4:5], 0, v0
-; GFX9-GISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
-; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
-; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: test_D139469_f16:
+; GFX9: ; %bb.0: ; %bb
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_mul_f16_e32 v1, 0x291e, v0
+; GFX9-NEXT: s_movk_i32 s4, 0x291e
+; GFX9-NEXT: v_cmp_gt_f16_e32 vcc, 0, v1
+; GFX9-NEXT: v_mov_b32_e32 v1, 0x211e
+; GFX9-NEXT: v_fma_f16 v0, v0, s4, v1
+; GFX9-NEXT: v_cmp_gt_f16_e64 s[4:5], 0, v0
+; GFX9-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
+; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-SDAG-LABEL: test_D139469_f16:
; GFX10-SDAG: ; %bb.0: ; %bb
@@ -123,9 +111,10 @@ define i32 @test_D139469_f16(half %arg) {
; GFX10-SDAG-NEXT: v_mov_b32_e32 v1, 0x211e
; GFX10-SDAG-NEXT: v_mul_f16_e32 v2, 0x291e, v0
; GFX10-SDAG-NEXT: v_fmac_f16_e32 v1, 0x291e, v0
-; GFX10-SDAG-NEXT: v_min_f16_e32 v0, v2, v1
-; GFX10-SDAG-NEXT: v_cmp_gt_f16_e32 vcc_lo, 0, v0
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX10-SDAG-NEXT: v_cmp_gt_f16_e32 vcc_lo, 0, v2
+; GFX10-SDAG-NEXT: v_cmp_gt_f16_e64 s4, 0, v1
+; GFX10-SDAG-NEXT: s_or_b32 s4, vcc_lo, s4
+; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-GISEL-LABEL: test_D139469_f16:
@@ -154,14 +143,17 @@ define <2 x i32> @test_D139469_v2f16(<2 x half> %arg) {
; GFX9-SDAG: ; %bb.0: ; %bb
; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-SDAG-NEXT: s_movk_i32 s4, 0x291e
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, 0x211e
; GFX9-SDAG-NEXT: v_pk_mul_f16 v1, v0, s4 op_sel_hi:[1,0]
-; GFX9-SDAG-NEXT: v_pk_fma_f16 v0, v0, s4, v2 op_sel_hi:[1,0,0]
-; GFX9-SDAG-NEXT: v_pk_min_f16 v1, v1, v0
; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, 0
; GFX9-SDAG-NEXT: v_cmp_gt_f16_e32 vcc, 0, v1
-; GFX9-SDAG-NEXT: v_cmp_lt_f16_sdwa s[4:5], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX9-SDAG-NEXT: v_cmp_lt_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, 0x211e
+; GFX9-SDAG-NEXT: v_pk_fma_f16 v0, v0, s4, v1 op_sel_hi:[1,0,0]
+; GFX9-SDAG-NEXT: v_cmp_gt_f16_e64 s[4:5], 0, v0
+; GFX9-SDAG-NEXT: v_cmp_lt_f16_sdwa s[8:9], v0, v2 src0_sel:WORD_1 src1_sel:DWORD
+; GFX9-SDAG-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
+; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
+; GFX9-SDAG-NEXT: s_or_b64 s[4:5], s[6:7], s[8:9]
; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[4:5]
; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -190,10 +182,13 @@ define <2 x i32> @test_D139469_v2f16(<2 x half> %arg) {
; GFX10-SDAG-NEXT: v_pk_mul_f16 v1, 0x291e, v0 op_sel_hi:[0,1]
; GFX10-SDAG-NEXT: v_pk_fma_f16 v0, 0x291e, v0, s4 op_sel_hi:[0,1,0]
; GFX10-SDAG-NEXT: v_mov_b32_e32 v2, 0
-; GFX10-SDAG-NEXT: v_pk_min_f16 v1, v1, v0
; GFX10-SDAG-NEXT: v_cmp_gt_f16_e32 vcc_lo, 0, v1
-; GFX10-SDAG-NEXT: v_cmp_lt_f16_sdwa s4, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX10-SDAG-NEXT: v_cmp_gt_f16_e64 s4, 0, v0
+; GFX10-SDAG-NEXT: v_cmp_lt_f16_sdwa s5, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+; GFX10-SDAG-NEXT: v_cmp_lt_f16_sdwa s6, v0, v2 src0_sel:WORD_1 src1_sel:DWORD
+; GFX10-SDAG-NEXT: s_or_b32 s4, vcc_lo, s4
+; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
+; GFX10-SDAG-NEXT: s_or_b32 s4, s5, s6
; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 1, s4
; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
;
diff --git a/llvm/test/CodeGen/AMDGPU/or.ll b/llvm/test/CodeGen/AMDGPU/or.ll
index 7759120273aa84..74969a68dd5756 100644
--- a/llvm/test/CodeGen/AMDGPU/or.ll
+++ b/llvm/test/CodeGen/AMDGPU/or.ll
@@ -1160,74 +1160,77 @@ define amdgpu_kernel void @or_i1(ptr addrspace(1) %out, ptr addrspace(1) %in0, p
; GFX6-LABEL: or_i1:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GFX6-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0xd
-; GFX6-NEXT: s_mov_b32 s3, 0xf000
-; GFX6-NEXT: s_mov_b32 s2, -1
-; GFX6-NEXT: s_mov_b32 s10, s2
-; GFX6-NEXT: s_mov_b32 s11, s3
+; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd
+; GFX6-NEXT: s_mov_b32 s11, 0xf000
+; GFX6-NEXT: s_mov_b32 s10, -1
+; GFX6-NEXT: s_mov_b32 s2, s10
+; GFX6-NEXT: s_mov_b32 s3, s11
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_mov_b32 s12, s6
; GFX6-NEXT: s_mov_b32 s13, s7
-; GFX6-NEXT: s_mov_b32 s14, s2
-; GFX6-NEXT: s_mov_b32 s15, s3
-; GFX6-NEXT: buffer_load_dword v0, off, s[8:11], 0
+; GFX6-NEXT: s_mov_b32 s14, s10
+; GFX6-NEXT: s_mov_b32 s15, s11
+; GFX6-NEXT: buffer_load_dword v0, off, s[0:3], 0
; GFX6-NEXT: buffer_load_dword v1, off, s[12:15], 0
-; GFX6-NEXT: s_mov_b32 s0, s4
-; GFX6-NEXT: s_mov_b32 s1, s5
+; GFX6-NEXT: s_mov_b32 s8, s4
+; GFX6-NEXT: s_mov_b32 s9, s5
; GFX6-NEXT: s_waitcnt vmcnt(1)
-; GFX6-NEXT: v_mul_f32_e32 v0, 1.0, v0
-; GFX6-NEXT: s_waitcnt vmcnt(0)
-; GFX6-NEXT: v_mul_f32_e32 v1, 1.0, v1
-; GFX6-NEXT: v_max_f32_e32 v0, v1, v0
; GFX6-NEXT: v_cmp_le_f32_e32 vcc, 0, v0
-; GFX6-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: v_cmp_le_f32_e64 s[0:1], 0, v1
+; GFX6-NEXT: s_or_b64 s[0:1], s[0:1], vcc
+; GFX6-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
+; GFX6-NEXT: buffer_store_dword v0, off, s[8:11], 0
; GFX6-NEXT: s_endpgm
;
; GFX8-LABEL: or_i1:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
-; GFX8-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x34
-; GFX8-NEXT: s_mov_b32 s3, 0xf000
-; GFX8-NEXT: s_mov_b32 s2, -1
-; GFX8-NEXT: s_mov_b32 s10, s2
-; GFX8-NEXT: s_mov_b32 s11, s3
+; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
+; GFX8-NEXT: s_mov_b32 s11, 0xf000
+; GFX8-NEXT: s_mov_b32 s10, -1
+; GFX8-NEXT: s_mov_b32 s2, s10
+; GFX8-NEXT: s_mov_b32 s3, s11
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_mov_b32 s12, s6
; GFX8-NEXT: s_mov_b32 s13, s7
-; GFX8-NEXT: s_mov_b32 s14, s2
-; GFX8-NEXT: s_mov_b32 s15, s3
-; GFX8-NEXT: buffer_load_dword v0, off, s[8:11], 0
+; GFX8-NEXT: s_mov_b32 s14, s10
+; GFX8-NEXT: s_mov_b32 s15, s11
+; GFX8-NEXT: buffer_load_dword v0, off, s[0:3], 0
; GFX8-NEXT: buffer_load_dword v1, off, s[12:15], 0
-; GFX8-NEXT: s_mov_b32 s0, s4
-; GFX8-NEXT: s_mov_b32 s1, s5
+; GFX8-NEXT: s_mov_b32 s8, s4
+; GFX8-NEXT: s_mov_b32 s9, s5
; GFX8-NEXT: s_waitcnt vmcnt(1)
-; GFX8-NEXT: v_mul_f32_e32 v0, 1.0, v0
-; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_mul_f32_e32 v1, 1.0, v1
-; GFX8-NEXT: v_max_f32_e32 v0, v1, v0
; GFX8-NEXT: v_cmp_le_f32_e32 vcc, 0, v0
-; GFX8-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; GFX8-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_cmp_le_f32_e64 s[0:1], 0, v1
+; GFX8-NEXT: s_or_b64 s[0:1], s[0:1], vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
+; GFX8-NEXT: buffer_store_dword v0, off, s[8:11], 0
; GFX8-NEXT: s_endpgm
;
; EG-LABEL: or_i1:
; EG: ; %bb.0:
-; EG-NEXT: ALU 1, @10, KC0[CB0:0-32], KC1[]
-; EG-NEXT: TEX 1 @6
-; EG-NEXT: ALU 4, @12, KC0[CB0:0-32], KC1[]
+; EG-NEXT: ALU 0, @12, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @8
+; EG-NEXT: ALU 0, @13, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @10
+; EG-NEXT: ALU 5, @14, KC0[CB0:0-32], KC1[]
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
; EG-NEXT: CF_END
; EG-NEXT: PAD
-; EG-NEXT: Fetch clause starting at 6:
-; EG-NEXT: VTX_READ_32 T1.X, T1.X, 0, #1
+; EG-NEXT: Fetch clause starting at 8:
; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1
-; EG-NEXT: ALU clause starting at 10:
-; EG-NEXT: MOV T0.X, KC0[2].Z,
-; EG-NEXT: MOV * T1.X, KC0[2].W,
+; EG-NEXT: Fetch clause starting at 10:
+; EG-NEXT: VTX_READ_32 T1.X, T1.X, 0, #1
; EG-NEXT: ALU clause starting at 12:
-; EG-NEXT: MAX_DX10 * T0.W, T0.X, T1.X,
-; EG-NEXT: SETGE_DX10 * T0.W, PV.W, 0.0,
+; EG-NEXT: MOV * T0.X, KC0[2].W,
+; EG-NEXT: ALU clause starting at 13:
+; EG-NEXT: MOV * T1.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 14:
+; EG-NEXT: SETGE_DX10 T0.W, T0.X, 0.0,
+; EG-NEXT: SETGE_DX10 * T1.W, T1.X, 0.0,
+; EG-NEXT: OR_INT * T0.W, PS, PV.W,
; EG-NEXT: AND_INT T0.X, PV.W, 1,
; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
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