[PATCH] D157694: [RISCV][MC]Add support for Binary MCExpr
Yunze Zhu(Thead) via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 24 19:44:30 PDT 2023
Yunzezhu updated this revision to Diff 553334.
Yunzezhu added a comment.
Herald added a subscriber: sunshaoce.
fixed a problem cause warning during compiling.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D157694/new/
https://reviews.llvm.org/D157694
Files:
llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
llvm/test/MC/RISCV/fixups-binary-expression.s
Index: llvm/test/MC/RISCV/fixups-binary-expression.s
===================================================================
--- /dev/null
+++ llvm/test/MC/RISCV/fixups-binary-expression.s
@@ -0,0 +1,31 @@
+# RUN: llvm-mc -triple riscv32 -mattr=+c -riscv-no-aliases < %s -show-encoding \
+# RUN: | FileCheck -check-prefix=CHECK-FIXUP %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c < %s \
+# RUN: | llvm-objdump -M no-aliases -d - \
+# RUN: | FileCheck -check-prefix=CHECK-INSTR %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c,+relax < %s \
+# RUN: | llvm-readobj -r - | FileCheck -check-prefix=CHECK-RELOC %s
+
+.LBB0:
+
+.LBB1:
+
+jal zero, .LBB0+16
+# CHECK-FIXUP: fixup A - offset: 0, value: .LBB0+16, kind: fixup_riscv_jal
+# CHECK-INSTR: jal zero, 0x10
+# CHECK-RELOC: R_RISCV_JAL
+
+beq a0, a1, .LBB1+32
+# CHECK-FIXUP: fixup A - offset: 0, value: .LBB1+32, kind: fixup_riscv_branch
+# CHECK-INSTR: beq a0, a1, 0x20
+# CHECK-RELOC: R_RISCV_BRANCH
+
+c.j .+32
+# CHECK: fixup A - offset: 0, value: .Ltmp0+32, kind: fixup_riscv_rvc_jump
+# CHECK-INSTR: c.j 0x28
+# CHECK-RELOC: R_RISCV_RVC_JUMP
+
+c.beqz a0, .-2
+# CHECK-FIXUP: fixup A - offset: 0, value: .Ltmp1-2, kind: fixup_riscv_rvc_branch
+# CHECK-INSTR: c.beqz a0, 0x8
+# CHECK-RELOC: R_RISCV_RVC_BRANCH
Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
===================================================================
--- llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
+++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
@@ -442,8 +442,10 @@
RelaxCandidate = true;
break;
}
- } else if (Kind == MCExpr::SymbolRef &&
- cast<MCSymbolRefExpr>(Expr)->getKind() == MCSymbolRefExpr::VK_None) {
+ } else if ((Kind == MCExpr::SymbolRef &&
+ cast<MCSymbolRefExpr>(Expr)->getKind() ==
+ MCSymbolRefExpr::VK_None) ||
+ Kind == MCExpr::Binary) {
if (MIFrm == RISCVII::InstFormatJ) {
FixupKind = RISCV::fixup_riscv_jal;
} else if (MIFrm == RISCVII::InstFormatB) {
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