[PATCH] D158790: [MDL] First full integration of MDL with LLVM

Thu Aug 24 16:05:17 PDT 2023

reidtatge created this revision.
Herald added subscribers: luke, mattd, gchakrabarti, sunshaoce, pmatos, asb, asavonic, foad, frasercrmck, kerbowa, luismarques, apazos, sameer.abuasal, steven.zhang, pengfei, s.egerton, Jim, mstorsjo, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, atanasyan, mgrang, edward-jones, zzheng, jrtc27, niosHD, sabuasal, simoncook, johnrusso, rbar, javed.absar, fedor.sergeev, kbarton, hiraditya, kristof.beyls, jgravelle-google, arichardson, sbc100, tpr, jvesely, nemanjai, sdardis, dylanmckay, jyknight, dschuff, arsenm, MatzeB.
Herald added a project: All.
reidtatge requested review of this revision.
Herald added subscribers: llvm-commits, wangpc, MaskRay, aheejin, jholewinski.
Herald added a project: LLVM.

This is the first public integration with the mainline LLVM Repo.  The
MDL language provides an alternate way (from TableGen) to describe a target
micro-architecture to the CodeGen and MC libraries. It provides all the
capability of Tablegen Schedules and Itineraries, but can efficiently
describe much more complex processors.

You can find the RFC with more detailed descriptions of this work at
[https://discourse.llvm.org/t/rfc-mdl-a-micro-architecture-description-language-for-llvm/66409] (from Nov 2022).
Detailed documentation about the design and the MDL language can be found in
the repo at llvm/docs/Mdl/.

This is the first integration of work that we plan to expand going
forward, and we'd like to land this to avoid bitrot and make the work
available to others. This integration is fully integrated - it can
extract microarchitecture information from TableGen, create equivalent
MDL descriptions, and compile and use that information in CodeGen and MC
libraries. This works for any target that has Schedules or Itineraries
(AArch64, AMDGPU, AMDGPU/R600, ARM, Hexagon, Lanai, Mips, PowerPC, RISCV,
Sparc, SystemZ, and X86).

MDL support is enabled using the LLVM_ENABLE_MDL cmake parameter. When enabled,
we build the MDL compiler and a tool to scrape necessary information from
tablegen files, then use this information in backend libraries instead
of using TableGen generated information. When not enabled (the default),
all the MDL-specific code is guarded by runtime flags that disable it.

We welcome comments and suggestions, and look forward to your feedback.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D158790

Files:
  llvm/CMakeLists.txt
  llvm/docs/Mdl/BundlePacking.md
  llvm/docs/Mdl/CmakeChanges.md
  llvm/docs/Mdl/ForwardingNetworks.md
  llvm/docs/Mdl/ItinerariesAndStages.md
  llvm/docs/Mdl/MDLCompilerDesignNotes.md
  llvm/docs/Mdl/MachineDescriptionNotes.md
  llvm/docs/Mdl/RFC.md
  llvm/docs/Mdl/ResourceGroups.md
  llvm/docs/Mdl/UsingTheMDLCompiler.md
  llvm/docs/Mdl/VirtualPredicateFunctions.md
  llvm/include/llvm/CodeGen/DFAPacketizer.h
  llvm/include/llvm/CodeGen/MDLHazardRecognizer.h
  llvm/include/llvm/CodeGen/ResourcePriorityQueue.h
  llvm/include/llvm/CodeGen/ScheduleHazardRecognizer.h
  llvm/include/llvm/CodeGen/TargetSchedule.h
  llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
  llvm/include/llvm/CodeGen/VLIWMachineScheduler.h
  llvm/include/llvm/Config/config.h.cmake
  llvm/include/llvm/MC/MCSubtargetInfo.h
  llvm/include/llvm/MC/MDLBundle.h
  llvm/include/llvm/MC/MDLInfo.h
  llvm/include/llvm/MC/MDLInstrInfo.h
  llvm/lib/CodeGen/DFAPacketizer.cpp
  llvm/lib/CodeGen/MachineCombiner.cpp
  llvm/lib/CodeGen/MachinePipeliner.cpp
  llvm/lib/CodeGen/MachineScheduler.cpp
  llvm/lib/CodeGen/MachineTraceMetrics.cpp
  llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
  llvm/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp
  llvm/lib/CodeGen/SelectionDAG/ScheduleDAGVLIW.cpp
  llvm/lib/CodeGen/TargetInstrInfo.cpp
  llvm/lib/CodeGen/TargetSchedule.cpp
  llvm/lib/CodeGen/TargetSubtargetInfo.cpp
  llvm/lib/CodeGen/VLIWMachineScheduler.cpp
  llvm/lib/MC/CMakeLists.txt
  llvm/lib/MC/MCSchedule.cpp
  llvm/lib/MC/MCSubtargetInfo.cpp
  llvm/lib/MC/MDLInstrInfo.cpp
  llvm/lib/MCA/InstrBuilder.cpp
  llvm/lib/Target/AArch64/AArch64Subtarget.cpp
  llvm/lib/Target/AArch64/CMakeLists.txt
  llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp
  llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
  llvm/lib/Target/AMDGPU/CMakeLists.txt
  llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
  llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp
  llvm/lib/Target/AMDGPU/MCTargetDesc/R600MCTargetDesc.cpp
  llvm/lib/Target/AMDGPU/R600Subtarget.cpp
  llvm/lib/Target/ARC/ARCSubtarget.cpp
  llvm/lib/Target/ARC/MCTargetDesc/ARCMCTargetDesc.cpp
  llvm/lib/Target/ARM/ARMScheduleM85.td
  llvm/lib/Target/ARM/ARMSubtarget.cpp
  llvm/lib/Target/ARM/CMakeLists.txt
  llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
  llvm/lib/Target/AVR/AVRSubtarget.cpp
  llvm/lib/Target/AVR/MCTargetDesc/AVRMCTargetDesc.cpp
  llvm/lib/Target/BPF/BPFSubtarget.cpp
  llvm/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.cpp
  llvm/lib/Target/CSKY/CSKYSubtarget.cpp
  llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCTargetDesc.cpp
  llvm/lib/Target/Hexagon/CMakeLists.txt
  llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp
  llvm/lib/Target/Hexagon/HexagonMachineScheduler.h
  llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
  llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
  llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
  llvm/lib/Target/Lanai/CMakeLists.txt
  llvm/lib/Target/Lanai/LanaiSubtarget.cpp
  llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.cpp
  llvm/lib/Target/LoongArch/LoongArchSubtarget.cpp
  llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCTargetDesc.cpp
  llvm/lib/Target/M68k/M68kSubtarget.cpp
  llvm/lib/Target/M68k/MCTargetDesc/M68kMCTargetDesc.cpp
  llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp
  llvm/lib/Target/MSP430/MSP430Subtarget.cpp
  llvm/lib/Target/Mips/CMakeLists.txt
  llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
  llvm/lib/Target/Mips/MipsSubtarget.cpp
  llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp
  llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp
  llvm/lib/Target/PowerPC/CMakeLists.txt
  llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
  llvm/lib/Target/PowerPC/PPCSubtarget.cpp
  llvm/lib/Target/RISCV/CMakeLists.txt
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
  llvm/lib/Target/RISCV/RISCVSubtarget.cpp
  llvm/lib/Target/Sparc/CMakeLists.txt
  llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp
  llvm/lib/Target/Sparc/SparcSubtarget.cpp
  llvm/lib/Target/SystemZ/CMakeLists.txt
  llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp
  llvm/lib/Target/SystemZ/SystemZHazardRecognizer.cpp
  llvm/lib/Target/SystemZ/SystemZSubtarget.cpp
  llvm/lib/Target/VE/MCTargetDesc/VEMCTargetDesc.cpp
  llvm/lib/Target/VE/VESubtarget.cpp
  llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.cpp
  llvm/lib/Target/WebAssembly/WebAssemblySubtarget.cpp
  llvm/lib/Target/X86/CMakeLists.txt
  llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
  llvm/lib/Target/X86/X86Subtarget.cpp
  llvm/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp
  llvm/lib/Target/XCore/XCoreSubtarget.cpp
  llvm/unittests/CodeGen/MFCommon.inc
  llvm/unittests/Target/AArch64/AArch64InstPrinterTest.cpp
  llvm/utils/MdlCompiler/CMakeLists.txt
  llvm/utils/MdlCompiler/cmake/ExternalAntlr4Cpp.cmake
  llvm/utils/MdlCompiler/cmake/FindANTLR.cmake
  llvm/utils/MdlCompiler/mdl.cpp
  llvm/utils/MdlCompiler/mdl.g4
  llvm/utils/MdlCompiler/mdl.h
  llvm/utils/MdlCompiler/mdl_dump.cpp
  llvm/utils/MdlCompiler/mdl_generate.cpp
  llvm/utils/MdlCompiler/mdl_generate.h
  llvm/utils/MdlCompiler/mdl_main.cpp
  llvm/utils/MdlCompiler/mdl_output.cpp
  llvm/utils/MdlCompiler/mdl_output.h
  llvm/utils/MdlCompiler/mdl_predicate.cpp
  llvm/utils/MdlCompiler/mdl_util.cpp
  llvm/utils/MdlCompiler/mdl_visitor.cpp
  llvm/utils/MdlCompiler/mdl_visitor.h
  llvm/utils/TableGen/SubtargetEmitter.cpp
  llvm/utils/TdScan/CMakeLists.txt
  llvm/utils/TdScan/arch.cpp
  llvm/utils/TdScan/debug.cpp
  llvm/utils/TdScan/output.cpp
  llvm/utils/TdScan/register.cpp
  llvm/utils/TdScan/scan.cpp
  llvm/utils/TdScan/scan.h