[PATCH] D158673: [SDAG][RISCV] Avoid neg instructions when lowering atomic_load_sub with a constant rhs

Thu Aug 24 12:52:01 PDT 2023

jrtc27 added a comment.

In D158673#4614877 <https://reviews.llvm.org/D158673#4614877>, @dtcxzyw wrote:

> In D158673#4614846 <https://reviews.llvm.org/D158673#4614846>, @jrtc27 wrote:
>
>> Can we not just teach SelectionDAG to handle ATOMIC_LOAD_SUB=Expand, ATOMIC_LOAD_ADD=Legal?
>
> I think we can let `RISCVTargetLowering::shouldExpandAtomicRMWInIR(atomicrmw sub)` return `Expand` and handle it in `RISCVTargetLowering::emitExpandAtomicRMW`.

That still makes it target-dependent, but the expansion at the IR or SelectionDAG level is target-independent. There is no reason we should have separate code for RISCV and AArch64. Sharing code rather than duplicating functionality is good practice when it makes sense, and I don't see a reason why it wouldn't here.

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  https://reviews.llvm.org/D158673/new/

https://reviews.llvm.org/D158673