[PATCH] D158673: [SDAG][RISCV] Avoid neg instructions when lowering atomic_load_sub with a constant rhs

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:2914
+  SDValue RHS = Op.getOperand(2);
+  if (RHS->getOpcode() == ISD::SIGN_EXTEND_INREG) {
+    RHS = RHS->getOperand(0);
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I don't think this safe to do this if you don't check that the VT in Operand 1 matches MemoryVT?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D158673/new/

https://reviews.llvm.org/D158673